Semiconductor device and method for manufacturing same

• US 9,099,553 B2
• Filed: 12/10/2012
• Issued: 08/04/2015
• Est. Priority Date: 01/13/2012
• Status: Active Grant

• Current Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Original Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Inventors: Masuda, Takeyoshi, Wada, Keiji, Hiyoshi, Toru
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): NGUYEN, CUONG B
• Application Number:
  US13/709,915
• Publication Number:
  US 20130181229A1
• Time in Patent Office: 967 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0485 Ohmic electrodes
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/6606 the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A MOSFET includes: a substrate having a first trench formed therein, the first trench opening on a side of one main surface; a gate insulating film; and a gate electrode. The substrate includes an n type source region, a p type body region, an n type drift region, and a p type deep region making contact with the body region and extending to a region deeper than the first trench. The first trench is formed such that a distance between the wall surface and the deep region increases with increasing distance from the main surface of the substrate.

Claims

1. A semiconductor device, comprising:

a substrate made of silicon carbide and having a first trench formed therein, said first trench opening on a side of one main surface;

a gate insulating film disposed on and in contact with a wall surface of said first trench; and

a gate electrode disposed on and in contact with said gate insulating film, said substrate including

a source region of a first conductivity type including said main surface of said substrate and said wall surface of said first trench,

a body region of a second conductivity type making contact with said source region and including said wall surface of said first trench,

a drift region of the first conductivity type making contact with said body region and including said wall surface of said first trench, and

a pair of deep regions of the second conductivity type making contact with said body region and said source region, and extending to a region deeper than said first trench, wherein said pair of deep regions is disposed at symmetrical positions with respect to a center of said first trench when viewed in cross-section,

said first trench being formed such that a distance between said wall surface and said deep region increases with increasing distance from said main surface of said substrate.

2. The semiconductor device according to claim 1, wherein said wall surface of said first trench forms an obtuse angle relative to said main surface of said substrate.

3. The semiconductor device according to claim 1, wherein

said substrate has a second trench formed therein, said second trench penetrating said source region and reaching said body region, opening on the side of said main surface, and being shallower than said first trench, and

said semiconductor device further comprises a contact electrode disposed on and in contact with a wall surface of said second trench.

4. The semiconductor device according to claim 3, wherein said substrate has said second trench formed therein, said second trench being shallower than a contact surface between said body region and said drift region.

5. The semiconductor device according to claim 3 wherein said contact electrode is disposed not to be on and in contact with said main surface of said substrate.

6. The semiconductor device according to claim 3, wherein a plane constituting said wall surface of said second trench is a plane crossing a {0001} plane.

7. The semiconductor device according to claim 3, wherein in a cross section along a thickness direction of said substrate including said first and second trenches, a fictitious straight line extending from said wall surface at a lowermost portion of said second trench in parallel with a {0001} plane crosses said wall surface of said first trench facing said second trench.

8. The semiconductor device according to claim 7, wherein in the cross section along the thickness direction of said substrate including said first and second trenches, said fictitious straight line crosses said wall surface of said first trench facing said second trench, without crossing said drift region.

9. The semiconductor device according to claim 1, wherein a plane constituting said main surface of said substrate is a plane having an off angle of 8°

or smaller relative to a {0001} plane.

10. The semiconductor device according to claim 1, wherein a plane constituting said wall surface of said first trench is a plane having an off angle of not less than 50°

and not more than 65°

relative to a {0001} plane.

11. The semiconductor device according to claim 1, wherein said deep region is formed to penetrate said source region and said body region and such that a contact surface thereof with said drift region is located closer to another main surface of said substrate than a bottom surface of said first trench, said another main surface is the main surface of said substrate opposite to said one main surface of said substrate.