Output impedance compensation of a pseudo-envelope follower power management system

• US 9,099,961 B2
• Filed: 09/10/2013
• Issued: 08/04/2015
• Est. Priority Date: 04/19/2010
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Kay, Michael R., Khlat, Nadim
• Primary Examiner(s): Nguyen, Patricia T
• Application Number:
  US14/022,858
• Publication Number:
  US 20140009227A1
• Time in Patent Office: 693 Days
• Field of Search: 330/127, 330/297, 455/127.1, 323/222
• US Class Current: 1/1
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 1/0244 Stepped control
• CPC Class Codes: H03F 1/025 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/42 Modifications of amplifiers to extend the bandwidth
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 2200/204 A hybrid coupler being used at the output of an amplifier circuit
• CPC Class Codes: H03F 2200/36 the amplifier comprising means for increasing the bandwidth
• CPC Class Codes: H03F 2200/375 Circuitry to compensate the offset being present in an amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/555 A voltage generating circuit being realised for biasing different circuit elements
• CPC Class Codes: H03F 2200/78 A comparator being used in a controlling circuit of an amplifier
• CPC Class Codes: H03F 2203/45526 the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45544 the IC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45594 the IC comprising one or more resistors, which are not biasing resistor
• CPC Class Codes: H03F 2203/45694 the LC comprising more than one shunting resistor
• CPC Class Codes: H03F 2203/45712 the LC comprising a capacitor as shunt
• CPC Class Codes: H03F 2203/45718 the LC comprising a resistor as shunt
• CPC Class Codes: H03F 2203/7221 the gated amplifier being switched on or off by a switch at the output of the amplifier
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/245 : with semiconductor devices only
• CPC Class Codes: H03F 3/3022 : CMOS common source output SEPP amplifiers H03F3/3008 takes precedence
• CPC Class Codes: H03F 3/45475 : using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/505 : with field-effect devices
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

A switch mode power supply converter, a parallel amplifier, and a parallel amplifier output impedance compensation circuit are disclosed. The switch mode power supply converter provides a switching voltage and generates an estimated switching voltage output, which is indicative of the switching voltage. The parallel amplifier generates a power amplifier supply voltage at a power amplifier supply output based on a compensated V_RAMP signal. The parallel amplifier output impedance compensation circuit provides the compensated V_RAMP signal based on a combination of a V_RAMP signal and a high frequency ripple compensation signal. The high frequency ripple compensation signal is based on a difference between the V_RAMP signal and the estimated switching voltage output.

Claims

1. Circuitry comprising:

a switch mode power supply converter configured to;

provide a switching voltage; and

generate an estimated switching voltage output, which is indicative of the switching voltage;

a parallel amplifier configured to generate a power amplifier supply voltage at a power amplifier supply output based on a compensated V_RAMP signal; and

a parallel amplifier output impedance compensation circuit configured to;

provide a high frequency ripple compensation signal based on a difference between a V_RAMP signal and the estimated switching voltage output; and

provide the compensated V_RAMP signal based on a combination of the V_RAMP signal and the high frequency ripple compensation signal.

2. The circuitry of claim 1 wherein the estimated switching voltage output is a delayed estimated switching voltage output and a controller is configured to temporally align the delayed estimated switching voltage output with respect to the V_RAMP signal.

3. The circuitry of claim 1 wherein the switch mode power supply converter comprises programmable delay circuitry configured to delay generation of the estimated switching voltage output by an alignment period to temporally align the estimated switching voltage output with the V_RAMP signal.

4. The circuitry of claim 3 wherein the alignment period is set to minimize a peak-to-peak ripple voltage on the power amplifier supply voltage.

5. The circuitry of claim 1 wherein the parallel amplifier output impedance compensation circuit comprises a subtracting circuit configured to provide an expected difference signal based on the difference between the V_RAMP signal and the estimated switching voltage output.

6. The circuitry of claim 5 wherein the parallel amplifier output impedance compensation circuit further comprises:

a Z_OUT compensation high pass filter configured to high pass filter the expected difference signal to generate an estimated high frequency ripple signal; and

a scalar circuit configured to scale the estimated high frequency ripple signal based on a scaling factor to generate the high frequency ripple compensation signal.

7. The circuitry of claim 1 wherein the parallel amplifier output impedance compensation circuit comprises a scalar circuit configured to scale an estimated high frequency ripple signal based on a scaling factor to generate the high frequency ripple compensation signal, wherein the estimated high frequency ripple signal is based on the difference between the V_RAMP signal and the estimated switching voltage output.

8. The circuitry of claim 7 wherein the scaling factor is based on a band of operation of a radio frequency power amplifier.

9. The circuitry of claim 7 wherein the scaling factor is based on an estimated inductance associated with the parallel amplifier between frequencies of 10 MHz and 30 MHz.

10. The circuitry of claim 7 wherein the scaling factor is based on a scaled parallel amplifier output current estimate associated with the parallel amplifier.

11. The circuitry of claim 7 wherein the parallel amplifier output impedance compensation circuit further comprises a tune circuit configured to provide the scaling factor based on a difference between the V_RAMP signal and the power amplifier supply voltage.

12. The circuitry of claim 11 wherein the parallel amplifier output impedance compensation circuit further comprises a subtracting circuit configured to subtract the power amplifier supply voltage from the compensated V_RAMP signal to provide a feedback signal, wherein the scaling factor is further based on the feedback signal.

13. The circuitry of claim 1 wherein the parallel amplifier output impedance compensation circuit further comprises a V_RAMP pre-distortion filter circuit configured to pre-distort the V_RAMP signal to provide a pre-filtered V_RAMP signal, wherein the combination of the V_RAMP signal and the high frequency ripple compensation signal is based on a combination of the pre-filtered V_RAMP signal and the high frequency ripple compensation signal.

14. The circuitry of claim 13 wherein the V_RAMP pre-distortion filter circuit is further configured to pre-distort the V_RAMP signal to provide a frequency response that is substantially flattened through a desired frequency range.

15. The circuitry of claim 13 wherein the V_RAMP pre-distortion filter circuit is further configured to pre-distort the V_RAMP signal to provide frequency peaking to compensate for a low pass filter effect of a combination of a power amplifier associated inductance and a power amplifier associated capacitance.

16. The circuitry of claim 13 wherein the parallel amplifier output impedance compensation circuit further comprises a summing circuit configured to add the pre-filtered V_RAMP signal to the high frequency ripple compensation signal to provide the compensated V_RAMP signal.

17. The circuitry of claim 1 wherein the parallel amplifier output impedance compensation circuit further comprises a pre-distortion subtraction circuit configured to subtract the high frequency ripple compensation signal from the V_RAMP signal to provide a non-filtered parallel amplifier output impedance compensation signal, such that the compensated V_RAMP signal is based on the non-filtered parallel amplifier output impedance compensation signal.

18. The circuitry of claim 1 wherein the parallel amplifier output impedance compensation circuit further comprises a V_RAMP post-distortion filter circuit configured to filter a non-filtered parallel amplifier output impedance compensation signal to provide the compensated V_RAMP signal, such that the non-filtered parallel amplifier output impedance compensation signal is based on the combination of the V_RAMP signal and the high frequency ripple compensation signal.

19. The circuitry of claim 18 wherein the V_RAMP post-distortion filter circuit is further configured to filter the non-filtered parallel amplifier output impedance compensation signal to provide a frequency response that is substantially flattened through a desired frequency range.

20. The circuitry of claim 18 wherein the V_RAMP post-distortion filter circuit is further configured to filter the non-filtered parallel amplifier output impedance compensation signal to provide frequency peaking to compensate for a low pass filter effect of a combination of a power amplifier associated inductance and a power amplifier associated capacitance.

21. The circuitry of claim 1 further comprising a coupling circuit coupled between the parallel amplifier and the power amplifier supply output.

22. The circuitry of claim 1 wherein the parallel amplifier is further configured to provide a parallel amplifier output voltage based on a difference between the compensated V_RAMP signal and the power amplifier supply voltage.

23. The circuitry of claim 1 wherein the switch mode power supply converter is configured as a multi-level charge pump buck converter.

24. A method comprising:

providing a switching voltage;

generating an estimated switching voltage output, which is indicative of the switching voltage;

generating a power amplifier supply voltage at a power amplifier supply output based on a compensated V_RAMP signal;

providing a high frequency ripple compensation signal based on a difference between a V_RAMP signal and the estimated switching voltage output; and

providing the compensated V_RAMP signal based on a combination of the V_RAMP signal and the high frequency ripple compensation signal.