Integrated driver and related method

• US 9,099,965 B2
• Filed: 12/01/2011
• Issued: 08/04/2015
• Est. Priority Date: 12/01/2010
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Zuffada, Maurizio, Pozzoni, Massimo, Contini, Angelo
• Primary Examiner(s): Kianni, Kaveh
• Application Number:
  US13/989,488
• Publication Number:
  US 20130308893A1
• Time in Patent Office: 1,342 Days
• Field of Search: 385/3, 385/14, 330/251
• US Class Current: 1/1
• CPC Class Codes: G02B 2006/12142 Modulator
• CPC Class Codes: G02B 2006/12145 Switch
• CPC Class Codes: G02B 6/1225 comprising photonic band-gap structures or photonic lattices
• CPC Class Codes: G02F 1/0121 Operation of devices; Circuit arrangements, not otherwise provided for in this subclass
• CPC Class Codes: G02F 1/0327 Operation of the cell; Circuit arrangements G02F1/05 takes precedence
• CPC Class Codes: G02F 1/212 Mach-Zehnder type
• CPC Class Codes: G02F 1/225 in an optical waveguide structure
• CPC Class Codes: H03F 1/22 by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 2200/45 the load of the amplifier being a capacitive element, e.g. CRT
• CPC Class Codes: H03F 2200/516 Some amplifier stages of an amplifier use supply voltages of different value
• CPC Class Codes: H03F 2203/30099 the pull transistor being gated by a switching element
• CPC Class Codes: H03F 2203/30132 the push transistor being gated by a switching element
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/3001 with field-effect transistors
• CPC Class Codes: H03F 3/45076 characterised by the way of implementation of the active amplifying circuit in the differential amplifier
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H04B 10/532 Polarisation modulation
• CPC Class Codes: H04B 10/616 : Details of the electronic signal processing in coherent optical receivers

Abstract

A driver circuit may include a first node (VA), and a first circuit to generate on the first node (VA) an inverted replica of an input signal (VIN) during driver switching between a first supply voltage (Vdd1) and ground, the inverted replica having a threshold voltage value based upon a reference voltage (Vref) greater than the first supply voltage (Vdd1). The driver circuit may include a cascode stage (M3) to be controlled by the reference voltage (Vref) and to be coupled between a second supply voltage (Vdd2) and the first node, a delay circuit (D) to generate a delayed replica of the input signal (VIN), an amplifier, and a switching network (M5, M6) to couple a control terminal of an active load transistor (M9) either to one of the reference voltage (Vref) or to ground, based upon the input signal (VIN).

Claims

1. A driver circuit comprising:

a first node;

a first circuit configured to generate on said first node an inverted replica of an input signal between a first supply voltage and a first reference voltage, the inverted replica having a threshold voltage value based upon a second reference voltage greater than the first supply voltage;

a cascode stage configured to be controlled by the second reference voltage and to be coupled between a second supply voltage and said first node;

a delay circuit configured to generate a delayed replica of the input signal;

an amplifier comprising

a first switch configured to be coupled to the first reference voltage and to be controlled by the delayed replica of the input signal,

a second switch configured to be controlled by the first supply voltage and comprising a conduction terminal to define an output terminal, and

an active load switch configured to be coupled between the output terminal and the second supply voltage and comprising a control terminal; and

a switching network configured to couple said control terminal of said active load switch to at least one of the first reference voltage and said first node based upon the input signal.

2. The driver circuit of claim 1 wherein the input signal comprises a square-wave input signal;

and wherein said switching network is configured to couple said control terminal of said active load transistor to at least one of the first reference voltage and said first node based upon a level of the square-wave input signal.

3. The driver circuit of claim 1 wherein said first circuit comprises:

a push-pull inverting stage configured to invert the input signal and to be coupled between the first supply voltage and the first reference voltage, and comprising a plurality of switches having a common node; and

a boost capacitor configured to be coupled between said common node of said plurality of switches and said first node and to be charged at a voltage to keep said cascode stage in a functioning mode.

4. The driver circuit of claim 1 wherein said delay circuit is configured to generate a delay to turn on said first switch after said active load switch has turned off.

5. The driver circuit of claim 1 wherein said active load switch has a first conductivity type;

and wherein said switching network comprises;

a first transistor having a second conductivity type, and configured to be controlled by the first supply voltage and to be coupled between said first node and said control terminal of said active load switch;

a second node;

a second transistor having the first conductivity type, and configured to be controlled by the input signal and to be coupled between said second node and the first reference voltage; and

a third transistor having the first conductivity type, and configured to be controlled by the first supply voltage and to be coupled between said second node and said control terminal of said active load switch.

6. The driver circuit of claim 1 wherein said first switch, and said second switch, each comprises a low-voltage metal-oxide-semiconductor field-effect transistor (MOSFET).

7. The driver circuit of claim 1 wherein said conduction terminal of said second switch is not in common with said first switch.

8. The driver circuit of claim 1 wherein said active load switch comprises a high-voltage active load switch.

9. The driver circuit of claim 1 wherein said amplifier comprises a class AB amplifier.

10. A differential driver circuit comprising:

a plurality of driver circuits configured to be input with respective complementary input signals and each driver circuit comprising

a first node,

a first circuit configured to generate on said first node an inverted replica of a respective complementary input signal between a first supply voltage and a first reference voltage, the inverted replica having a threshold voltage value based upon a second reference voltage greater than the first supply voltage,

a cascode stage configured to be controlled by the second reference voltage and to be coupled between a second supply voltage and said first node,

a delay circuit configured to generate a delayed replica of the respective complementary input signal,

an amplifier comprising

a first switch configured to be coupled to the first reference voltage and to be controlled by the delayed replica of the respective complementary input signal,

a second switch configured to be controlled by the first supply voltage and comprising a conduction terminal to define an output terminal, and

an active load switch configured to be coupled between the output terminal and the second supply voltage and comprising a control terminal, and

a switching network configured to couple said control terminal of said active load transistor to at least one of the first reference voltage and said first node based upon the respective complementary input signal.

11. The differential driver circuit of claim 10 wherein the respective complementary input signal comprises a square-wave input signal;

and wherein said switching network is configured to couple said control terminal of said active load transistor to at least one of the first reference voltage and said first node based upon a level of the square-wave input signal.

12. The differential driver circuit of claim 10 wherein said first circuit comprises:

a push-pull inverting stage configured to invert the respective complementary input signal and to be coupled between the first supply voltage and the first reference voltage, and comprising a plurality of switches having a common node; and

a boost capacitor configured to be coupled between said common node of said plurality of switches and said first node and to be charged at a voltage to keep said cascode stage in a functioning mode.

13. The differential driver circuit of claim 10 wherein said delay circuit is configured to generate a delay to turn on said first switch after said active load switch has turned off.

14. The differential driver circuit of claim 10 wherein each driver circuit from said plurality thereof is identical.

15. A Mach-Zehnder optical modulator comprising:

a modulator; and

a driver configured to control the said modulator and comprising

a first node,

a first circuit configured to generate on said first node an inverted replica of an input signal between a first supply voltage and a first reference voltage, the inverted replica having a threshold voltage value based upon a second reference voltage greater than the first supply voltage,

a cascode stage configured to be controlled by the second reference voltage and to be coupled between a second supply voltage and said first node,

a delay circuit configured to generate a delayed replica of the input signal,

an amplifier comprising

a first switch configured to be coupled to the first reference voltage and to be controlled by the delayed replica of the input signal,

a second switch configured to be controlled by the first supply voltage and comprising a conduction terminal to define an output terminal, and

an active load switch configured to be coupled between the output terminal and the second supply voltage and comprising a control terminal, and

a switching network configured to couple said control terminal of said active load switch to at least one of the first reference voltage and said first node based upon the input signal.

16. The Mach-Zehnder optical modulator of claim 15 wherein the input signal comprises a square-wave input signal;

and wherein said switching network is configured to couple said control terminal of said active load transistor to at least one of the first reference voltage and said first node based upon a level of the square-wave input signal.

17. The Mach-Zehnder optical modulator of claim 15 wherein said first circuit comprises:

a push-pull inverting stage configured to invert the input signal and to be coupled between the first supply voltage and the first reference voltage, and comprising a plurality of switches having a common node; and

a boost capacitor configured to be coupled between said common node of said plurality of switches and said first node and to be charged at a voltage to keep said cascode stage in a functioning mode.

18. The Mach-Zehnder optical modulator of claim 15 wherein said delay circuit is configured to generate a delay to turn on said first switch after said active load switch has turned off.

19. The Mach-Zehnder optical modulator of claim 15 wherein said active load switch has a first conductivity type;

and wherein said switching network comprises;

a first transistor having a second conductivity type, and configured to be controlled by the first supply voltage and to be coupled between said first node and said control terminal of said active load switch;

a second node;

a second transistor having the first conductivity type, and configured to be controlled by the input signal and to be coupled between said second node and the first reference voltage; and

a third transistor having the first conductivity type, and configured to be controlled by the first supply voltage and to be coupled between said second node and said control terminal of said active load switch.