Ring oscillator circuit and method

• US 9,099,995 B2
• Filed: 03/14/2013
• Issued: 08/04/2015
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Hinrichs, Jeffrey Mark, Chen, Luis
• Primary Examiner(s): Johnson, Ryan
• Application Number:
  US13/804,366
• Publication Number:
  US 20140266475A1
• Time in Patent Office: 873 Days
• Field of Search: 331/57, 331/175, 331/186, 331/17, 331/34, 323/273, 323/274, 323/280, 323/281, 323/279
• US Class Current: 1/1
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Oscillator circuits and methods are disclosed. In an embodiment, a circuit includes a voltage controlled oscillator (VCO) and a regulator coupled to a supply input of the VCO. The circuit also includes an oscillation dampening circuit coupled to an output of the regulator. A resistance or a capacitance of the oscillation dampening circuit is configured to vary based on current provided to the VCO.

Claims

1. A circuit comprising:

a voltage controlled oscillator (VCO) having a supply input;

a regulator having an output coupled to the supply input of the VCO;

an oscillation dampening circuit comprising a first dampening portion and a second dampening portion, wherein the first dampening portion is coupled between the output of the regulator and a positive supply node providing a current to the supply input of the VCO, wherein an impedance of the oscillation dampening circuit is configured to vary based on the current provided to the supply input of the VCO, and wherein the second dampening portion is coupled between the output of the regulator and a negative supply node; and

a current mirror circuit configured to mirror the current provided to the supply input of the VCO, wherein the second dampening portion is coupled to the current mirror circuit.

2. The circuit of claim 1, wherein the oscillation dampening circuit causes a zero of a loop gain of the regulator to substantially cancel a pole at a control node coupled to the supply input of the VCO.

3. The circuit of claim 2, wherein the oscillation dampening circuit comprises a first transistor, wherein the first transistor has a gate that is biased to operate the first transistor in a triode mode to provide a variable resistance, the variable resistance being substantially proportional to a square root of the amount of current that is provided to the VCO.

4. The circuit of claim 3, wherein the current mirror circuit has an input coupled to the output of the regulator and an output coupled to the gate of the first transistor and wherein the current mirror circuit is configured to provide a voltage to the gate of the first transistor, the voltage corresponding to the square root of the amount of current that is provided to the VCO.

5. The circuit of claim 1, wherein the regulator comprises an operational amplifier having an output coupled to a gate of a VCO supply transistor, wherein a drain of the VCO supply transistor is coupled to the supply input of the VCO to provide the current to the supply input of the VCO.

6. The circuit of claim 5, further comprising a feedback loop to provide a voltage at the supply input of the VCO to an input of the operational amplifier.

7. The circuit of claim 6, wherein the VCO provides an output of a phase locked loop (PLL) and wherein the regulator has an input that is coupled to an output of a loop filter of the PLL.

8. The circuit of claim 1, wherein the oscillation dampening circuit comprises a resistance-capacitance (RC) circuit.

9. A method for dampening oscillations at a voltage controlled oscillator, the method comprising:

receiving a voltage based on a current provided to the voltage controlled oscillator (VCO);

dampening oscillations using a dampening circuit to provide a variable impedance, wherein the dampening circuit comprises a first dampening portion and a second dampening portion, wherein the first dampening portion is coupled between an output of a regulator and a positive supply node providing the current to the VCO, wherein the variable impedance is responsive to the voltage at the output of the regulator that controls the current provided to the VCO, and wherein the second dampening portion is coupled between the output of the regulator and a negative supply node; and

mirroring the current provided to the VCO via a current mirror circuit, wherein the second dampening portion is coupled to the current mirror circuit.

10. The method of claim 9, wherein the voltage received at the variable impedance further comprises the voltage received at a gate of a transistor in a resistance-capacitance (RC) circuit coupled to the output of the regulator.

11. The method of claim 10 wherein the variable impedance comprises at least one of a variable resistance or a variable capacitance in the RC circuit.

12. The method of claim 11 wherein the at least one of a variable resistance or a variable capacitance comprises a variable resistance in the RC circuit.

13. The method of claim 9, wherein the variable impedance is configurable to cause a zero of a loop gain of the regulator to substantially cancel a pole at a control node of the VCO.

14. A non-transitory computer readable medium comprising instructions wherein the instructions, when executed by a processor cause the processor to control operations comprising:

receiving a voltage based on a current provided to a voltage controlled oscillator (VCO);

dampening oscillations using a dampening circuit to provide a variable impedance, wherein the dampening circuit comprises a first dampening portion and a second dampening portion, wherein the first dampening portion is coupled between an output of a regulator and a positive supply node providing the current to the VCO, wherein the variable impedance is responsive to the voltage at the output of the regulator that controls the current provided to the VCO, and wherein the second dampening portion is coupled between the output of the regulator and a negative supply node; and

mirroring the current provided to the VCO via a current mirror circuit, wherein the second dampening portion is coupled to the current mirror circuit.

15. The non-transitory computer readable medium of claim 14 wherein the voltage received at the variable impedance further comprises the voltage received at a gate of a transistor in a resistance-capacitance (RC) circuit coupled to the output of the regulator.

16. The non-transitory computer readable medium of claim 15 wherein the variable impedance in the RC circuit causes a zero of a loop gain of the regulator to substantially cancel a pole at a control node of the VCO.

17. The non-transitory computer readable medium of claim 16 wherein the variable impedance comprises a variable capacitance in the RC circuit, the variable capacitance causing a zero of a loop gain of the regulator to substantially cancel a pole at a control node of the VCO.

18. An apparatus comprising:

means for generating an oscillating signal;

means for regulating a supply input of the means for generating;

means for dampening oscillations, the means for dampening comprising a first dampening portion and a second dampening portion, wherein the first dampening portion is coupled between an output of the means for regulating and a positive supply node providing a current to the means for generating, wherein an impedance of the means for dampening is configured to vary based on the current that is provided to the means for generating, and wherein the second dampening portion is coupled between the output of the regulator and a negative supply node; and

means for mirroring the current provided to the means for generating, wherein the second dampening portion is coupled to the means for mirroring.

19. The apparatus of claim 18 where the means for dampening substantially cancels a pole at the means for generating by causing a zero of a loop gain at the means for regulating.

20. The apparatus of claim 19 wherein the impedance comprises at least one of a variable resistance or a variable capacitance configurable to vary substantially proportionally to a square root of the amount of current that is provided to the means for generating.

21. A circuit comprising:

an oscillation dampening circuit comprising a first dampening portion and a second dampening portion, wherein the first dampening portion is coupled to an output of a regulator and includes;

a first capacitor having a first terminal coupled to the output of the regulator and having a second terminal; and

a first transistor having a gate terminal, a drain terminal, and a source terminal, wherein the drain terminal of the first transistor is coupled to the second terminal of the first capacitor, wherein the source terminal of the first transistor is coupled to a positive supply node, wherein the gate terminal of the first transistor is coupled to an output of a current mirror circuit that is configured to mirror a supply current of a voltage controlled oscillator (VCO), wherein the second dampening portion is coupled between the output of the regulator and a negative supply node, and wherein the second dampening portion is coupled to the current mirror circuit.

22. The circuit of claim 21, wherein the oscillation dampening circuit causes a zero of a loop gain of the regulator to substantially cancel a pole at a control node of the VCO.

23. The circuit of claim 22, wherein the oscillation dampening circuit first transistor provides a variable resistance substantially proportional to a square root of the amount of current that is provided to the VCO.

24. The circuit of claim 21, wherein the second dampening portion comprises:

a second capacitor having a first connection and a second connection; and

a second transistor having a gate connection, a source connection, and a drain connection, wherein the second capacitor first connection is coupled to the output of the regulator, wherein the second capacitor second connection is coupled to the second transistor drain, and wherein the second transistor gate is coupled to the current mirror circuit.