Semiconductor integrated circuit device

• US 9,100,034 B2
• Filed: 03/10/2014
• Issued: 08/04/2015
• Est. Priority Date: 03/11/2013
• Status: Expired due to Fees

• Current Assignee: Clarion Co., Ltd. (Faurecia SA), Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Oshima, Takashi, Matsuura, Tatsuji, Okuda, Yuichi, Nakane, Hideo, Yamamoto, Takaya, Kimura, Keisuke
• Primary Examiner(s): WILLIAMS, HOWARD L
• Application Number:
  US14/203,052
• Publication Number:
  US 20140253352A1
• Time in Patent Office: 512 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H03M 1/002 Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
• CPC Class Codes: H03M 1/0609 at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error
• CPC Class Codes: H03M 1/0639 using dither, e.g. using triangular or sawtooth waveforms for increasing resolution H03M1/201
• CPC Class Codes: H03M 1/1038 by storing corrected or correction values in one or more digital look-up tables H03M1/1057 takes precedence
• CPC Class Codes: H03M 1/109 for dc performance, i.e. static testing H03M1/1085 takes precedence
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H03M 1/14 Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
• CPC Class Codes: H03M 1/38 sequentially only, e.g. successive approximation type converting more than one bit per step H03M1/14
• CPC Class Codes: H03M 1/44 Sequential comparisons in series-connected stages with change in value of analogue signal
• CPC Class Codes: H03M 1/46 with digital/analogue converter for supplying reference values to converter
• CPC Class Codes: H03M 1/56 Input signal compared with linear ramp

Abstract

A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.

Claims

1. A semiconductor integrated circuit device comprising:

an A/D conversion unit;

a digital correction unit operable to output an A/D conversion result by performing digital correcting to a digital output received from the A/D conversion unit; and

a holding unit operable to hold a test signal to the A/D conversion unit,

wherein the A/D conversion unit is of a charge sharing type and operable to perform successive approximation,

wherein, at the time of a test, a test signal with the same analog value from the holding unit is inputted into the A/D conversion unit in a first period and a second period different from the first period, a first dither signal is inputted into the A/D conversion unit in the first period, and an A/D conversion correction coefficient is determined, on the basis of a first digital correction result in the digital correction unit to a first digital output from the A/D conversion unit in the first period and a second digital correction result in the digital correction unit to a second digital output from the A/D conversion unit in the second period, and

wherein, at the time of a normal operation, the digital correcting is performed with the use of the A/D conversion correction coefficient determined at the time of the test.

2. The semiconductor integrated circuit device according to claim 1,

wherein the holding unit is provided with an operational amplifier and acts as a D/A converter operable to generate the test signal.

3. The semiconductor integrated circuit device according to claim 2,

wherein the operational amplifier also acts as an input buffer circuit for the A/D conversion unit at the time of the normal operation.

4. The semiconductor integrated circuit device according to claim 1,

wherein the holding unit is a sample hold circuit.

5. The semiconductor integrated circuit device according to claim 1,

wherein, in the test period, a second dither signal different from the first dither signal is inputted into the A/D conversion unit in the second period.

6. The semiconductor integrated circuit device according to claim 1,

wherein the A/D conversion unit comprises:

a first sampling circuit;

a second sampling circuit; and

a conversion unit,

wherein the A/D conversion unit operates by repetition of a first timing and a second timing,

wherein, in the first timing, the first digital output is generated in the conversion unit by A/D converting the first analog signal as the test signal held in the first sampling circuit, and a second analog signal as the test signal from the holding unit is held in the second sampling circuit,

wherein, in the second timing, the second digital output is generated in the conversion unit by A/D converting the second analog signal held in the second sampling circuit, and a first analog signal from the holding unit is held in the first sampling circuit, and

wherein the digital correction unit comprises;

a gain correction circuit operable to correct the gain error caused by the difference between the first sampling circuit and the second sampling circuit.

7. The semiconductor integrated circuit device according to claim 2,

wherein the D/A converter comprises:

a first D/A conversion circuit operable to generate the first dither signal; and

a second D/A conversion circuit operable to generate the test signal, and

wherein, in the first period at the time of the test, the first dither signal superimposed on the test signal is inputted to the A/D conversion unit from the holding unit.

8. A semiconductor integrated circuit device comprising:

an A/D conversion unit;

a digital correction unit operable to output an A/D conversion result by performing digital correcting to a digital output received from the A/D conversion unit; and

a holding unit operable to hold a test signal to the A/D conversion unit,

wherein the digital correction unit comprises;

a delay circuit,

wherein the A/D conversion unit is of a charge sharing type and operable to perform successive approximation,

wherein a test signal with the same analog value from the holding unit is inputted into the A/D conversion unit in a first period and a second period different from the first period, a first dither signal is inputted into the A/D conversion unit in the first period, and an A/D conversion correction coefficient is calculated, on the basis of a first digital correction result in the digital correction unit to a first digital output from the A/D conversion unit in the first period and a second digital correction result in the digital correction unit to a second digital output from the A/D conversion unit in the second period, and

wherein the A/D conversion correction coefficient is calculated by comparing the first digital correction result with the second digital correction result, with the aid of delay processing by the delay circuit.

9. A semiconductor integrated circuit device comprising:

an A/D conversion unit of a charge sharing type operable to perform successive approximation;

a digital correction unit operable to output an A/D conversion result by performing digital correcting to a digital output received from the A/D conversion unit; and

a holding unit operable to hold a test signal,

wherein a test signal of a common value from the holding unit is inputted into the A/D conversion unit in a first period and a second period different from the first period, and

wherein an A/D conversion correction coefficient for the digital correction unit is calculated, on the basis of a first digital correction result in the digital correction unit in the first period and a second digital correction result in the digital correction unit in the second period.

10. The semiconductor integrated circuit device according to claim 9,

wherein the A/D conversion unit comprises:

a first sampling circuit;

a second sampling circuit; and

a conversion unit,

wherein the A/D conversion unit operates by repetition of a first timing and a second timing,

wherein, in the first timing, the first digital output is generated in the conversion unit by A/D converting the first analog signal held in the first sampling circuit, and a second analog signal from the holding unit is held in the second sampling circuit, and

wherein, in the second timing, the second digital output is generated in the conversion unit by A/D converting the second analog signal held in the second sampling circuit, and a first analog signal from the holding unit is held in the first sampling circuit.

11. The semiconductor integrated circuit device according to claim 10,

wherein the digital correction unit comprises a gain correction circuit operable to correct the gain error caused by the difference between the first sampling circuit and the second sampling circuit.