Data processing systems and methods providing error correction

• US 9,100,054 B2
• Filed: 03/07/2012
• Issued: 08/04/2015
• Est. Priority Date: 03/10/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Kijun, Kong, Junjin, Lim, Sejin, Kim, Jaehong, Son, Hong-Rak, Kim, Yong-June
• Primary Examiner(s): Blair, April Y
• Assistant Examiner(s): GANDHI, DIPAKKUMAR B
• Application Number:
  US13/414,002
• Publication Number:
  US 20120233518A1
• Time in Patent Office: 1,245 Days
• US Class Current: 1/1
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2933 using a block and a convolutional code H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/3738 with judging correct decoding

Abstract

A method may be provided to detect and correct data errors in a data system where a data message has been encoded with outer parity bits based on the data message using an outer encoding technique to provide an outer codeword and with inner parity bits based on the outer codeword using an inner encoding technique different than the outer encoding technique to provide an inner codeword. The method may include using the inner parity bits and an inner decoding technique corresponding to the inner encoding technique to perform inner decoding of the inner codeword. Responsive to performing inner decoding of the inner codeword without error, the data message may be extracted from a result of inner decoding the inner codeword without using the outer parity bits to decode the result of inner decoding the inner codeword. Related systems are also discussed.

Claims

1. A solid state drive of a data processing system, the solid state drive comprising:

a plurality of memory channels of the solid state drive configured to store data, wherein each memory channel includes a plurality of nonvolatile memory storage devices; and

a concatenated decoder coupled to the plurality of memory channels of the solid state drive, wherein the concatenated decoder is configured to detect and correct errors of inner words and outer words transferred from the plurality of memory channels, wherein the concatenated decoder comprises,

an inner decoder configured to decode the inner words to output the outer words each formed of a message and parity data on the message;

an outer decoder configured to decode the outer words to output decoded messages to an external device; and

a decoder controller configured to control the inner and outer decoders, wherein the decoder controller is configured to extract the messages from the outer words to output the messages to the external device without processing through the outer decoder when a decoding operation of the inner decoder is performed successfully,

wherein the decoder controller is configured to provide an output of the inner decoder to an input of the inner decoder and the inner decoder is configured to iteratively perform the decoding operation up to a maximum loop number when the decoder operation of the inner decoder fails,

wherein if the decoding operation of the inner decoder fails after the inner decoding operation is iterated by the maximum loop number, the decoder controller is configured to provide the output of the inner decoder to the outer decoder,

wherein the inner decoder includes a plurality of inner decoders each corresponding to a respective one of the memory channels of the solid state drive, wherein the outer decoder includes a plurality of outer decoders, and wherein the plurality of outer decoders includes a number of the outer decoders that is less than a number of the memory channels of the solid state drive and that is less than a number of the inner decoders.

2. The solid state drive of claim 1, wherein the decoder controller is configured to decide a decoding order of the outer words output from the inner decoder according to a priority of the outer words, and to provide the outer words to the outer decoders according to the decoding order.

3. The solid state drive of claim 1, wherein a decoding technique of the inner decoder is different from a decoding technique of the outer decoder.

4. The solid state drive of claim 3, wherein the inner decoder uses one of a BCH (Bose, Chaudhuri, Hocquenghem) code, an RS (Reed-Solomon) code, a convolutional code, an LDPC (Low Density Parity Check) code, or a turbo code.

5. The solid state drive of claim 3, wherein the outer decoder uses one of a BCH (Bose, Chaudhuri, Hocquenghem) code, an RS (Reed-Solomon) code, or a CRC (cyclic redundancy check) code.

6. The solid state drive of claim 1, wherein the concatenated decoder further includes an error detecting unit configured to check whether errors of the outer words output from the inner decoder are corrected normally.

7. The solid state drive of claim 6, wherein the decoder controller is configured to provide the outer words to the outer decoder when a checking result of the error detecting unit indicates that an error correction operation fails.

8. The solid state drive of claim 1, further comprising:

a concatenated encoder configured to encode data to be transferred respectively through the memory channels, wherein the concatenated encoder includes an outer encoder configured to generate outer codewords by encoding data to be transferred respectively via the memory channels, and an inner encoder configured to generate inner codewords by encoding the outer codewords.

9. The solid state drive of claim 1 wherein the decoder controller is configured to decide a decoding order of the outer words output from the inner decoder according to a priority of the outer words, and to provide the outer words to the outer decoders according to the decoding order.

10. The solid state drive of claim 1 wherein the nonvolatile memory storage devices of a respective memory channel comprise NAND flash memory devices.

11. A solid state drive of a data processing system, the solid state drive comprising:

a plurality of memory channels of the solid state drive configured to store data, wherein each memory channel includes a plurality of nonvolatile memory storage devices; and

a concatenated decoder coupled to the plurality of memory channels of the solid state drive, wherein the concatenated decoder is configured to detect and correct errors of inner words and outer words transferred from the plurality of memory channels, wherein the concatenated decoder comprises,

an inner decoder configured to decode the inner words to output the outer words each formed of a message and parity data on the message;

an outer decoder configured to decode the outer words to output decoded messages to an external device; and

a decoder controller configured to control the inner and outer decoders, wherein the decoder controller is configured to extract the messages from the outer words to output the messages to the external device without processing through the outer decoder when a decoding operation of the inner decoder is performed successfully,

wherein the inner decoder includes a plurality of inner decoders each corresponding to a respective one of the memory channels of the solid state drive, wherein the outer decoder includes a plurality of outer decoders, and wherein the plurality of outer decoders includes a number of the outer decoders that is less than a number of the memory channels of the solid state drive and that is less than a number of the inner decoders.