Predict computing platform memory power utilization

• US 9,104,409 B2
• Filed: 04/01/2010
• Issued: 08/11/2015
• Est. Priority Date: 06/06/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Dodeja, Rakesh, Chandwani, Neelam, Hiremath, Chetan, Mukherjee, Udayan, Ambrose, Anthony
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): CHANG, VINCENT WEN-LIANG
• Application Number:
  US12/752,955
• Publication Number:
  US 20100191997A1
• Time in Patent Office: 1,958 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3225 of memory devices

Abstract

A method to reduce memory power consumption for a computing platform includes inspecting an operating parameter associated with a resource of the computing platform that is updated by the resource of the computing platform during runtime of the computing platform. Memory power utilization is then predicted for the computing platform during the runtime of the computing platform based at least in part on the operating parameter. A current power state of at least one memory module resident on the computing platform is transitioned to one of a plurality of power states based on the predicting of the memory power utilization.

Claims

1. A method to reduce memory power consumption for a computing platform, the method comprising:

during runtime of the computing platform, inspecting an operating parameter associated with a resource of the computing platform that is updated by the resource of the computing platform during the runtime of the computing platform;

predicting a change from a current level of memory power utilization by the computing platform to another level of memory power utilization by the computing platform during the runtime of the computing platform, the predicting including evaluating, based on the inspecting the operating parameter, a statistical parameter of a statistical prediction algorithm, wherein the operating parameter includes a network traffic parameter, a processing element memory allocation parameter or a memory access pattern parameter; and

transitioning a current power state of at least one memory module resident on the computing platform to one of a plurality of power states based on the predicting of the change from the current level of memory power utilization.

2. The method of claim 1, wherein inspecting the operating parameter comprises monitoring a memory location storing the operating parameter, wherein the memory location includes at least one of a register, a table in memory, or a buffer.

3. The method of claim 1, wherein the resource comprises at least one of a processing element, a network interface, or a memory controller.

4. The method of claim 1, wherein the statistical prediction algorithm is determined during a given period of time that begins as the computing platform is initially powered-up.

5. The method of claim 1, wherein the statistical prediction algorithm is determined during a given period of time and tuned periodically during the runtime of the computing platform.

6. The method of claim 5, wherein the statistical parameter includes at least one of memory requests made to a memory controller for the at least one memory module, memory capacity utilization for a processing element on the computing platform and network bandwidth on at least one communication link between the computing platform and a network.

7. The method of claim 1, further comprising:

obtaining a configuration parameter from a memory controller for the at least one memory module, the configuration parameter to include at least one usage configuration for the at least one memory module selected from the following group of;

memory interleaving, memory mirroring, memory sparing and rank order allocation.

8. The method of claim 1, wherein the plurality of power states includes an offline state, an online state, a standby state, or a suspend state.

9. The method of claim 1, wherein the at least one memory module is a fully buffered dual inline memory module (FB-DIMM).

10. The method of claim 9, wherein transitioning the FB-DIMM to one of the plurality of power states results in another FB-DIMM resident on the computing platform also transitioning to the same power state.

11. A non-transitory machine-accessible storage medium storing content, which, when executed by a machine resident on a computing platform causes the machine to perform:

monitoring an operating parameter associated with a resource of the computing platform during runtime of the computing platform by inspecting a memory location that is updated by the resource of the computing platform during runtime of the computing platform;

predicting a change from a current level of memory power utilization by the computing platform to another level of memory power utilization by the computing platform during the runtime of the computing platform, the predicting including evaluating, based on the inspecting the operating parameter, a statistical parameter of a statistical prediction algorithm, wherein the operating parameter includes a network traffic parameter, a processing element memory allocation parameter or a memory access pattern parameter; and

transitioning a current power state of at least one memory module resident on the computing platform to one of a plurality of power states based on the predicting of the change from the current level of memory power utilization.

12. The non-transitory machine-accessible storage medium of claim 11, wherein the memory location comprises at least one of a register, a table in memory, or a buffer.

13. The non-transitory machine-accessible storage medium of claim 11, wherein the resource comprises at least one of a processing element, a network interface, or a memory controller.

14. The non-transitory machine-accessible storage medium of claim 11, wherein the statistical prediction algorithm is determined during a given period of time that begins as the computing platform is initially powered-up.

15. The non-transitory machine-accessible storage medium of claim 11, wherein the statistical prediction algorithm is determined during a given period of time and tuned periodically during the runtime of the computing platform.

16. The non-transitory machine-accessible storage medium of claim 15, wherein the statistical parameter includes at least one of memory requests made to a memory controller for the at least one memory module, memory capacity utilization for a processing element on the computing platform and network bandwidth on at least one communication link between the computing platform and a network.

17. The non-transitory machine-accessible storage medium of claim 11, wherein the plurality of power states includes an offline state, an online state, a standby state, and a suspend state.