Variable precision floating point multiply-add circuit

• US 9,104,474 B2
• Filed: 12/28/2012
• Issued: 08/11/2015
• Est. Priority Date: 12/28/2012
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kaul, Himanshu, Anders, Mark A., Mathew, Sanu K., Allmon, Randy L., Krishnamurthy, Ram K., Hasenplaugh, William C., Enoch, Jonathan
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US13/730,390
• Publication Number:
  US 20140188968A1
• Time in Patent Office: 956 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 2207/382 Reconfigurable for different fixed word lengths multigauge devices G06F2207/3828
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 9/30014 with variable precision

Abstract

Embodiments of the present invention may provide methods and circuits for energy efficient floating point multiply and/or add operations. A variable precision floating point circuit may determine the certainty of the result of a multiply-add floating point calculation in parallel with the floating-point calculation. The variable precision floating point circuit may use the certainty of the inputs in combination with information from the computation, such as, binary digits that cancel, normalization shifts, and rounding, to perform a calculation of the certainty of the result. A floating point multiplication circuit may determine whether a lowest portion of a multiplication result could affect the final result and may induce a replay of the multiplication operation when it is determined that the result could affect the final result.

Claims

1. A variable precision floating point circuit comprising:

a variable precision mantissa unit to selectively operate in any one of a plurality of precision modes wherein in each precision mode a level of parallelism in the variable precision floating point circuit is inversely proportional to a level of precision,

multiple exponent units to selectively operate in one of a plurality of parallelism modes corresponding to a selected precision mode,

and certainty calculation units to calculate certainty bounds of one or more outputs of the variable precision unit.

2. The circuit of claim 1, wherein the variable precision mantissa unit includes a multiplier that multiplies first and second inputs to generate a multiplication result in a carry-save format, the multiplier is configured to operate in the plurality of precision modes that includes at least one of a high precision mode, a middle precision mode and a low precision mode.

3. The circuit of claim 2, wherein in the middle precision and low precision modes, the multiplier is delineated into a plurality of zones and partial products that do not lie along a predetermined diagonal are set to zero or not used.

4. The circuit of claim 2, wherein the variable precision mantissa unit further includes an alignment shifter that aligns a third input with the multiplication result.

5. The circuit of claim 2, wherein the variable precision mantissa unit further includes an alignment shifter that right shifts a third input to be aligned with the multiplication result according to the selected precision mode, the right shift amount(s) are determined by the exponent units based on exponents of the first, second and third inputs.

6. The circuit of claim 5, wherein the variable precision mantissa unit further includes a reconfigurable adder to convert carry-save outputs to 2'"'"'s complement format.

7. The circuit of claim 6, wherein the reconfigurable adder is a reconfigurable sparse carry-tree adder.

8. The circuit of claim 6, wherein the variable precision mantissa unit further includes a shifter to perform normalization shift, the shift amount(s) are determined by a variable precision leading zero anticipation unit.

9. The circuit of claim 8, wherein the shifter is a left shifter to perform normalization left shift.

10. The circuit of claim 8 further comprising:

a round-up incrementer coupled to an output of the shifter, said round-up incrementer which is also used to increment an output of the shifter for a subtraction operation to maintain said output in 2'"'"'s complement format.

11. The circuit of claim 10 further comprising:

a plurality of XOR negation circuits to negate only a plurality of lower significant bits of a shifted addend supplied to said adder for the subtraction operation.

12. The circuit of claim 1, wherein the certainty calculation units operate in parallel with the exponent units to calculate output certainty based on input certainties, input numbers, the selected precision mode, and whether multiply-add or multiply-subtract operations are to be performed.

13. The circuit of claim 1 further comprising:

a certainty tracking circuit to calculate a certainty value as a power of 2 representing how may bits of the mantissa in the mantissa unit are certain relative to the exponent in the exponent units.

14. The circuit of claim 13 wherein said certainty tracking circuit is to calculate an error term due to a product of error bounds for operands to the floating point circuit and compensate for said error term by adding a “

1”

to a compressor column in the multiplier to reduce error bounds of a result for the floating point circuit.

15. A system comprising:

a multiply-add circuit comprising;

a variable precision mantissa unit to selectively operate in anyone of a plurality of precision modes,

multiple exponent units to selectively operate in one of a plurality of parallelism corresponding to a selected precision mode,

and certainty calculation units to calculate certainty bounds of output(s) of the variable precision unit.

16. The system of claim 15, wherein the variable precision mantissa unit includes a multiplier that multiplies a first and second inputs to generate a multiplication result in a carry-save format, the multiplier is configured to operate in the plurality of precision modes that includes at least one of a high precision mode, a middle precision mode and a low precision mode.

17. The system of claim 16, wherein in the middle precision and low precision modes, the multiplier is delineated into a plurality of zones and partial products that do not lie along a predetermined diagonal are set to zero or not used.

18. The system of claim 17, wherein the variable precision mantissa unit further includes an alignment shifter that right shifts a third input to be aligned with the multiplication result according to the selected precision mode, the right shift amount(s) are determined by the exponent units based on exponents of the first, second and third inputs.

19. The system of claim 18, wherein the variable precision mantissa unit further includes a reconfigurable sparse carry-tree adder to convert carry-save outputs to 2'"'"'s complement format.

20. The system of claim 19, wherein the variable precision mantissa unit further includes a shifter to perform normalization shift, the shift amount(s) are determined by a variable precision leading zero anticipation unit.

21. The system of claim 15, wherein the certainty calculation units operate in parallel with the exponent units to calculate output certainty based on input certainties, input numbers, the selected precision mode, and whether multiply-add or multiply-subtract operations are to be performed.

22. A n-bit by n-bit multiplier circuit comprising:

a parallelogram configured to set carries of a predetermined number (k) of least significant bits (LSBs) of a multiplication product to zero for a multiplication operation, and

a detection circuit configured to induce a replay of the multiplication operation by the multiplier to generate a full multiplication result, wherein inducing a replay of the multiplication operation is dependent on the multiplication product for the multiplication operation.

23. The n-bit by n-bit multiplier circuit of claim 22, wherein the parallelogram comprises a plurality of points that each represents a 3-2 full carry save adder (CSA) with carries pushed to the left.

24. The n-bit by n-bit multiplier circuit of claim 22, wherein if the detection circuit determines that the carries of k LSBs within a carry region could propagate a carry into a results region, the detection circuit induces the replay utilizing a full-multiplier array.

25. The n-bit by n-bit multiplier circuit of claim 22, wherein the detection circuit detects whether all upper n−

k−

log, (2k) bits of a carry region are ones (1s), the carry region is determined by a bit-width of the multiplication result and k LSBs.

26. The n-bit by n-bit multiplier circuit of claim 25, wherein the detection circuit further includes an adder to add lower log₂ (2k) bits of the carry region.

27. The n-bit by n-bit multiplier circuit of claim 22, wherein inputs to be multiplied are booth encoded.