Method and apparatus for memory management

• US 9,104,548 B2
• Filed: 01/20/2012
• Issued: 08/11/2015
• Est. Priority Date: 01/21/2011
• Status: Active Grant

• Current Assignee: Multi-Flex Circuits Pty., Ltd.
• Original Assignee: Blackbird Technology Holdings, Inc (Haystack Technologies, Inc.)
• Inventors: Norair, John Peter
• Primary Examiner(s): Tseng, Cheng-Yuan
• Assistant Examiner(s): Ahmed, Zubair
• Application Number:
  US13/354,513
• Publication Number:
  US 20120191901A1
• Time in Patent Office: 1,299 Days
• Field of Search: 711 1-200
• US Class Current: 1/1
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 2212/20 Employing a main memory using a specific memory technology
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

One or more circuits of a device may comprise a memory. A first portion of a first block of the memory may store program code and/or program data, a second portion of the first block may store an index associated with a second block of the memory, and a third portion of the first block may store an indication of a write status of the first portion. Each bit of the third portion of the first block may indicate whether an attempt to write data to a corresponding one or more words of the first portion of the first block has failed since the last erase of the corresponding one or more words of the first portion of the first block. Whether data to be written to a particular virtual address is written to the first block or the second block may depend on the write status of the first block and the second block.

Claims

1. A method comprising:

performing by one or more circuits comprising memory, in response to an instruction to write data to said memory;

if a first portion of a first block of said memory has been erased more recently than it has been written to, writing data to said first portion of said first block of said memory without first erasing said first block of said memory;

if said first portion of said first block of said memory has been written to more recently than it has been erased, and a first portion of a second block of said memory has been erased more recently than it has been written to, writing data to said first portion of said second block of memory without first erasing said second block of said memory; and

if said first portion of said first block of said memory has been written to more recently than it has been erased, and said first portion of said second block of said memory has been written to more recently than it has been erased, recombining said first block of said memory and said second block of said memory and, subsequent to said recombining, writing said data to said first portion of said first block of said memory;

storing an index associated with a said second block of said memory in said first block of said memory.

2. The method of claim 1, wherein said recombining said first block of said memory and said second block of said memory comprises:

copying at least some of the contents of said first block of said memory to said second block of said memory;

erasing said first block of said memory; and

associating an index with said second block of said memory, wherein said index was associated with said first block of said memory prior to said recombining.

3. The method of claim 1, comprising performing by said one or more circuits in response to said instruction to write said data to said memory:

converting a virtual memory address of said instruction to an index associated with said first block of said memory.

4. The method of claim 3, comprising performing by said one or more circuits in response to said instruction to write said data to said memory:

determining a physical address of said first block of said memory based on said index associated with said first block of said memory.

6. The method of claim 1, wherein said memory is a NAND flash memory.

7. The method of claim 1, wherein erasing any memory cell of said first block of said memory requires erasing all memory cells of said first block of said memory.

8. The method of claim 1, wherein erasing any memory cell of said second block of said memory requires erasing all memory cells of said second block of said memory.

5. A method comprising:

performing by one or more circuits comprising memory in response to an instruction to write said data to said memory;

if a first portion of a first block of said memory has been erased more recently than it has been written to, writing data to said first portion of said first block of said memory without first erasing said first block of said memory;

if said first portion of said first block of said memory has been written to more recently than it has been erased, and a first portion of a second block of said memory has been erased more recently than it has been written to, writing data to said first portion of said second block of memory without first erasing said second block of said memory;

if said first portion of said first block of said memory has been written to more recently than it has been erased, and said first portion of said second block of said memory has been written to more recently than it has been erased, recombining said first block of said memory and said second block of said memory and, subsequent to said recombining, writing said data to said first portion of said first block of said memory;

reading an index associated with said second block of said memory from said first block of said memory; and

determining a physical address of said second block of said memory using said index of said second block of said memory.

9. A system comprising:

one or more circuits comprising a memory, wherein;

a first portion of a first block of said memory stores program code and/or program data;

a second portion of said first block of said memory stores an index associated with a second block of said memory; and

a third portion of said first block of said memory stores an indication of a write status of said first portion of said first block of said memory;

a first portion of said second block of said memory stores program code and/or program data;

a second portion of said second block of said memory stores an index associated with said first block of said memory;

a third portion of said second block of said memory stores an indication of a write status of said first portion of said second block of said memory.

10. The system of claim 9, wherein each bit of said third portion of said first block of said memory indicates whether an attempt to write data to a corresponding one or more words of said first portion of said first block of said memory has failed since the last erase of said corresponding one or more words of said first portion of said first block of said memory.

11. The system of claim 9, wherein said one or more circuits are operable to:

receive an instruction to write data to said memory;

write said data to a word of said first portion of said first block of said memory if said word of said first portion of said first block of said memory has been erased more recently than it has been written to; and

write said data to a word of a first portion of said second block of said memory if said word of said first portion of said first block of said memory has been written to more recently than it has been erased.

12. The system of claim 9, wherein said one or more circuits are operable to:

receive an instruction to write data to said memory;

detect that (i) a word of said first portion of said first block of said memory has been written to more recently than it has been erased, and (ii) a word of said first portion of said second block of said memory has been written to more recently than it has been erased; and

recombine said first block of said memory and said second block of said memory in response to said detection.

13. The system of claim 12, wherein said recombining said first block of said memory and said second block of said memory comprises:

copying at least some of the contents of said first block of said memory to said second block of said memory;

erasing said first block of said memory; and

associating said second block of said memory with an index formerly associated with said first block of said memory.

14. The system of claim 13, wherein said recombining said first block of said memory and said second block of said memory comprises changing an index stored in said second portion of said second block of said memory.

15. The system of claim 14, wherein said index stored in said second portion of said second block of said memory is changed to an index associated with a third block of said memory.

16. The system of claim 14, wherein said index stored in said second portion of said second block of said memory is changed to an index formerly associated with said second block of said memory.

17. The system of claim 14, wherein said new index is randomly selected from a plurality of available indices.

18. The system of claim 9, wherein:

said memory is a NAND flash memory; and

said first block is located at a single, particular physical address of said NAND flash memory.