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NAND flash based content addressable memory

  • US 9,104,551 B2
  • Filed: 01/24/2013
  • Issued: 08/11/2015
  • Est. Priority Date: 11/09/2012
  • Status: Active Grant
First Claim
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1. A method of operating a memory system, the memory system including an array of non-volatile memory cells arranged into a NAND type of architecture, including a plurality NAND strings and a plurality word lines spanning the NAND strings, each of the word lines connected to a corresponding one of the memory cells thereof, the method comprising:

  • receiving a search data pattern from a host device to which the memory system is connected;

    biasing a first plurality of the word lines according to the search data pattern; and

    concurrently determining those of the NAND strings that conduct in response to the first plurality of the word lines biased according to the search data pattern being applied thereto.

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