Cache memory for hybrid disk drives

• US 9,104,580 B1
• Filed: 03/23/2011
• Issued: 08/11/2015
• Est. Priority Date: 07/27/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Meir, Avraham
• Primary Examiner(s): Li, Aimee
• Assistant Examiner(s): Tsang, Kenneth
• Application Number:
  US13/069,406
• Time in Patent Office: 1,602 Days
• Field of Search: 711/103, 711/E12.008, 711/170
• US Class Current: 1/1
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A method for data storage in a data storage system, which includes a main storage device and a non-volatile memory, includes assessing quality levels of respective memory blocks of the non-volatile memory. One or more of the memory blocks whose assessed quality levels are lower than a predefined quality threshold are identified. The identified memory blocks are assigned to serve as read cache memory. Data is read from the main storage device via the read cache memory, including the assigned memory blocks.

Claims

1. A method for data storage, comprising:

in a data storage system that includes a main storage device and a non-volatile memory, assessing a respective quality level of each memory block of a plurality of memory blocks of the non-volatile memory;

identifying a first subset of memory blocks of the plurality of memory blocks, wherein the quality level of each memory block of the first subset of memory blocks is less than a predefined quality threshold;

adjusting the predefined quality threshold to generate an updated quality threshold, wherein a second number of memory blocks included in a second subset of memory blocks of the plurality of memory blocks is different than a first number of memory blocks included in the first subset of memory blocks, and wherein each memory block included in the second subset of memory blocks has an assessed quality level less than the updated quality threshold;

assigning the second subset of memory blocks to serve as read cache memory; and

reading data from the main storage device via the read cache memory, including the assigned memory blocks;

wherein assessing the respective quality level of each memory block of the plurality of memory blocks in the non-volatile memory includes determining a respective number of post-programming errors in each memory block;

wherein the predefined quality threshold corresponds to a number of post-programming errors in a given memory block; and

wherein determining the respective number of post-programming errors in each memory block includes determining the respective number of post-programming errors in each memory block responsive to a determination that a period of time has elapsed since a first group of memory cells in each memory block has been programmed prior to programming a second group of memory cells in each memory block, and responsive to a determination that a temperature change has occurred since the first group of memory cells in each memory block has been programmed.

2. The method according to claim 1, wherein the non-volatile memory is partitioned into at least the read cache memory and a write cache memory, and further comprising assigning at least one memory block of the plurality of memory blocks whose assessed quality level is greater than the updated quality threshold to the write cache memory.

3. The method according to claim 1, and comprising storing the data in the memory blocks belonging to the read cache memory at a first storage density, and storing the data in the memory blocks that do not belong to the read cache memory at a second storage density that is smaller than the first storage density.

4. The method according to claim 1, wherein the main storage device comprises a Hard Disk Drive (HDD) and wherein the non-volatile memory comprises a solid state memory device.

5. The method according to claim 1, wherein assessing the respective quality level comprises reporting the quality level of at least one memory block of the plurality of memory blocks from a memory controller coupled to the non-volatile memory to a host, and wherein assigning the second subset of memory blocks comprises allocating the second subset of memory blocks to the read cache memory by the host based on the reported quality level of the at least one memory block, and indicating the memory blocks assigned to the read cache memory from the host to the memory controller.

6. An apparatus, comprising:

an interface for communicating at least with a non-volatile memory; and

a processor, configured to;

assess a respective quality level of each memory block of a plurality of memory blocks of the non-volatile memory;

identify a first subset of memory blocks of the plurality of memory blocks, wherein the quality level of each memory block of the first subset of memory blocks is less than a predefined quality threshold;

adjust the predefined quality threshold to generate an updated quality threshold, wherein a second number of memory blocks included in a second subset of memory blocks of the plurality of memory blocks is different than a first number of memory blocks included in the first subset of memory blocks, and wherein each memory block included in the second subset of memory blocks has an assessed quality level less than the updated quality threshold; and

assign the second subset of memory blocks to serve as read cache memory for readout from a main storage device;

wherein to assess the respective quality level of each memory block in the non-volatile memory, the processor is further configured to determine a respective number of post-programming errors of each memory block;

wherein the predefined quality threshold corresponds to a number of post-programming errors in a given memory block; and

wherein to determine the respective number of post-programming errors in each memory block, the processor is further configured to determine the respective number of post-programming errors in each memory block responsive to a determination that a period of time has elapsed since a first group of memory cells in each memory block has been programmed prior to programming a second group of memory cells in each memory block, and responsive to a determination that a temperature change has occurred since the first group of memory cells in each memory block has been programmed.

7. The apparatus according to claim 6, wherein the non-volatile memory is partitioned into at least the read cache memory and a write cache memory, and wherein the processor is configured to assign at least one memory block of the plurality of memory blocks whose assessed quality level is greater than the updated quality threshold to the write cache memory.

8. The apparatus according to claim 6, wherein the processor is configured to extract the quality levels from production test results that identify low-quality memory blocks.

9. The apparatus according to claim 8, wherein the processor is configured to extract the quality levels by identifying the memory blocks that are indicated by the test data as expected to endure less than a predefined number of Programming and Erasure (P/E) cycles.

10. The apparatus according to claim 6, wherein the processor is configured to store the data in the memory blocks belonging to the read cache memory at a first storage density, and to store the data in the memory blocks that do not belong to the read cache memory at a second storage density that is smaller than the first storage density.

11. The apparatus according to claim 6, wherein the main storage device comprises a Hard Disk Drive (HDD) and wherein the non-volatile memory comprises a solid state memory device.

12. The apparatus according to claim 6, wherein the processor comprises:

a memory controller, which is coupled to the non-volatile memory and is configured to assess the respective quality level of each memory block of the plurality of memory blocks and to report the quality level of at least one memory block of the plurality of memory blocks over a host interface; and

a host, which is configured to allocate the second subset of memory blocks to the read cache memory based on the quality level of the at least one memory block reported by the memory controller, and to indicate the second subset of memory blocks assigned to the read cache memory to the memory controller.

13. A data storage apparatus, comprising:

a main storage device;

a non-volatile memory; and

a processor, configured to;

assess a respective quality level of each memory block of a plurality of memory blocks of the non-volatile memory;

identify a first subset of memory blocks of the plurality of memory blocks, wherein the quality level of each memory block of the first subset of memory blocks is less than a predefined quality threshold;

adjust the predefined quality threshold to generate an updated quality threshold, wherein a second number of memory blocks included in a second subset of memory blocks of the plurality of memory blocks is different than a first number of memory blocks included in the first subset of memory blocks, and wherein each memory block included in the second subset of memory blocks has an assessed quality level less than the updated quality threshold; and

assign the second subset of memory blocks to serve as read cache memory for readout from the main storage device;

wherein to assess the respective quality level of each memory block in the non-volatile memory, the processor is further configured to determine a respective number of post-programming errors of each memory block;

wherein the predefined quality threshold corresponds to a number of post-programming errors in a given memory block; and

wherein to determine the respective number of post-programming errors in each memory block, the processor is further configured to determine the respective number of post-programming errors in each memory block responsive to a determination that a period of time has elapsed since a first group of memory cells in each memory block has been programmed prior to programming a second group of memory cells in each memory block, and responsive to a determination that a temperature change has occurred since the first group of memory cells in each memory block has been programmed.