Selective remedial action based on category of detected error for a memory read

• US 9,104,595 B2
• Filed: 03/12/2013
• Issued: 08/11/2015
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sah, Suneeta
• Primary Examiner(s): Chase, Shelly A
• Application Number:
  US13/797,681
• Publication Number:
  US 20140281805A1
• Time in Patent Office: 882 Days
• Field of Search: 714/6.13, 714/746, 714/763, 714/807, 714/42
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check

Abstract

Embodiments of apparatus, methods, systems, computer-readable storage media and devices are described herein for determining an error category for a detected error in data read from a volatile memory; and selectively performing or causing an additional remedial action based at least in part on the error category determined. In various embodiments, the determining and the performing or causing may be undertaken in response to the correcting. The memory may be volatile or non-volatile memory. Other embodiments may be described and/or claimed.

Claims

1. An apparatus comprising a memory controller configured to perform or cause a remedial action to correct a detected error in data read from a memory, determine an error category for the detected error in data read from the memory, and selectively perform or cause an additional remedial action based at least in part on the error category determined, wherein the determination and the performance or causation of the additional remedial action are undertaken in response to the correction of the detected error in the data read from the memory.

2. The apparatus of claim 1, wherein the memory controller is further configured to categorize the detected error as transient in response to a determination that the detected error is absent from the memory after the correction.

3. The apparatus of claim 2, wherein the memory controller is further configured to categorize the detected error as transient in response to a determination that the detected error is absent from the memory after a write of the error-correct data back to the memory.

4. The apparatus of claim 1, wherein the apparatus further comprises a basic input/output system (“

BIOS”

), and the memory controller is further configured to cause the BIOS to be informed of the detected error, in response to detection of an error in the memory by the memory controller after the correction.

5. The apparatus of claim 1, wherein the apparatus further comprises an operating system, and the memory controller is further configured to cause the operating system to be informed of the detected error, in response to detection of an error in the memory by the memory controller after the correction.

6. The apparatus of claim 1, wherein the memory controller is further configured to assert a System Management Interrupt (“

SMI”

) in response to detection of an error in the memory by the memory controller after the correction.

7. The apparatus of claim 1, wherein the memory comprises volatile memory.

8. The apparatus of claim 7, wherein the memory comprises dynamic random access memory (“

DRAM”

).

9. The apparatus of claim 8, wherein the memory comprises a DRAM cache line.

10. At least one non-transitory storage medium comprising instructions stored therein, wherein the instructions, in response to execution by a controller, cause the controller to:

detect an error in data read from a memory;

perform or cause a remedial action to correct the detected error in the data read from the memory;

determine an error category for the detected error; and

selectively perform or cause an additional remedial action based at least in part on the error category determined;

wherein the determination and the performance or causation of the additional remedial action are undertaken in response to the correction.

11. The at least one non-transitory storage medium of claim 10, wherein the instructions, in response to execution by the controller, cause the controller to categorize the detected error as transient in response to a determination that the detected error is absent from the memory after the correction.

12. The at least one non-transitory storage medium of claim 11, wherein the instructions, in response to execution by the controller, cause the controller to categorize the detected error as transient in response to a determination that the detected error is absent from the memory after a write of the error-correct data back to the memory.

13. The at least one non-transitory storage medium of claim 10, wherein the instructions, in response to execution by the controller, cause a basic input/output system (“

BIOS”

) of a system hosting the controller to be informed of the detected error, in response to detection of an error in the memory after the correction.

14. The at least one non-transitory storage medium of claim 10, wherein the instructions, in response to execution by the controller, cause an operating system of a system hosting the controller to be informed of the detected error, in response to detection of an error in the memory after the correction.

15. The at least one non-transitory storage medium of claim 10, wherein the instructions, in response to execution by the controller, cause the controller to assert a System Management Interrupt (“

SMI”

) in response to detection of an error in the memory after the correction.

16. The at least one non-transitory storage medium of claim 10, wherein the memory comprises volatile memory.

17. The at least one non-transitory storage medium of claim 16, wherein the memory comprises dynamic random access memory (“

DRAM”

).

18. A computer-implemented method, comprising:

detecting, by a computing device, an error in data read from a memory;

performing or causing a remedial action, by the computing device, to correct the detected error in the data read from the memory;

determining, by the computing device, an error category for the detected error; and

selectively performing or causing, by the computing device, an additional remedial action based at least in part on the error category determined;

wherein the determining and the performing or causing the additional remedial action are undertaken in response to the correcting.

19. The computer-implemented method of claim 18, further comprising categorizing, by the computing device, the detected error as transient in response to a determination that the detected error is absent from the memory after the correction.

20. The computer-implemented method of claim 19, further comprising categorizing, by the computing device, the detected error as transient in response to a determination that the detected error is absent from the memory after a write of the error-corrected data back to the memory.