Power aware retention flop list analysis and modification

• US 9,104,824 B1
• Filed: 04/30/2013
• Issued: 08/11/2015
• Est. Priority Date: 04/30/2013
• Status: Expired due to Fees

• Current Assignee: Jasper Design Automation, Inc. (Cadence Group)
• Original Assignee: Jasper Design Automation, Inc. (Cadence Group)
• Inventors: Loh, Lawrence, Jobstmann, Barbara, Caldeira, Antonio Celso Jr., Mazzawi, Jamil R.
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US13/874,398
• Time in Patent Office: 833 Days
• Field of Search: 716100-101, 716/106, 716108-109, 716110-111, 716132-134
• US Class Current: 1/1
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/3323 using formal methods, e.g. equivalence checking or property checking
• CPC Class Codes: G06F 30/337 Design optimisation
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A register transfer level (RTL) design is received which models a digital circuit in terms of the flow of digital signals. A power intent description is received which may include a description of power domains, identification of retention flops for each power domain, a list of isolation signals, and power switch definitions. A transformed RTL is produced accounting for functionality described in the power intent description. The transformed RTL includes flops designated as retention flops and non-retention flops. A retention flop module analyzes the flops to ensure that flops are properly designated as retention or non-retention flops. A verification module performs power aware sequential equivalence checking on various RTL and power intent descriptions to verify that RTL and power intent description outputs behave the same when accounting for power states.

Claims

1. A computer implemented method for retention flop list analysis, the method comprising:

receiving a first register transfer level (RTL) circuit model of a circuit design, the first RTL circuit model including a plurality of flops;

receiving a power intent description of the circuit design, the power intent description including a retention flop list for a power domain;

analyzing the first RTL circuit model and the power intent description to identify a retention flop of the plurality of flops for modification; and

enhancing functionality of the plurality of flops by verifying the plurality of flops and performing a propagation analysis using a retention flop analysis mechanism that is coupled with at least one processor of a computing system and determines whether a conversion between the retention flop and a non-retention flop is to be performed based in part or in whole upon state information in the power domain and further by performing the conversion that has been determined to be performed while reducing a number of nets to be analyzed by the retention flop analysis mechanism coupled with the at least one processor in the analysis.

2. The method of claim 1, wherein the method further comprising modifying the retention flop list by removing the retention flop from the retention flop list based at least in part upon results of analyzing the first RTL circuit model to restore the power domain to an accurate state, and one or more non-retention flops of the plurality of flops are identified for modification to retention flops.

3. The method of claim 2, wherein the one or more non-retention flops are identified through unknown binary number propagation analysis, and the retention flop removed from the retention flop list is replaced with a non-retention flop of the one or more retention flops.

4. The method of claim 3, wherein the unknown binary number propagation analysis is performed in parallel on a plurality of non-retention flops.

5. The method of claim 2, wherein modifying the retention flop list comprises adding one or more non-retention flops to the retention flop list.

6. The method of claim 2, wherein one or more retention flops in the retention flop list are identified for modification to non-retention flops.

7. The method of claim 6, wherein modifying the retention flop list comprises removing at least one flop from the retention flop list.

8. The method of claim 6, wherein an accurate state comprises values of the plurality of flops being same before and after a power-sequence is performed.

9. The method of claim 8, further comprising:

verifying the accurate state of the plurality of flops after a power-on delay has occurred for a first time period.

10. The method of claim 9, wherein the retention flop is identified by verifying the accurate state of the plurality of flops utilizing the retention list after the retention flop has been removed from the retention list.

11. The method of claim 9, further comprising:

increasing the duration of the first time period responsive to receiving an input from a user indicating the accurate state of the first plurality of flops should be verified after a longer power-on delay.

12. A non-transitory computer-readable storage medium comprising computer program code for retention flop list analysis, the program code comprising a sequence of instructions which, when executed by at least one processor, causes the at least one processor to perform a group of acts for retention flop list analysis, the group of acts including:

receiving a first register transfer level (RTL) circuit model of a circuit design, the first RTL circuit model including a plurality of flops;

receiving a power intent description of the circuit design, the power description including a retention flop list for a power domain;

analyzing the second RTL circuit model to identify a retention flop of the plurality of flops for modification; and

enhancing functionality of the plurality of flops by verifying the plurality of flops and performing a propagation analysis using a retention flop analysis mechanism that is coupled with at least one processor of a computing system and determines whether a conversion between the retention flop and a non-retention flop is to be performed based in part or in whole upon state information in the power domain and further by performing the conversion that has been determined to be performed while reducing a number of nets to be analyzed by the retention flop analysis mechanism coupled with the at least one processor in the analysis.

13. The computer-readable storage medium of claim 12, wherein one or more non-retention flops of the plurality of flops are identified for modification to retention flops, and the group of acts further includes modifying the retention flop list by removing retention flop from the retention flop list based at least in part upon results of analyzing the first RTL circuit model to restore the power domain to an accurate state.

14. The computer-readable storage medium of claim 13, wherein the one or more non-retention flops are identified through unknown binary number propagation analysis, and the retention flop removed from the retention flop list is replaced with a non-retention flop of the one or more retention flops.

15. The computer-readable storage medium of claim 14, wherein the unknown binary number propagation analysis is performed in parallel on a plurality of non-retention flops.

16. The computer-readable storage medium of claim 13, wherein modifying the retention flop list comprises adding one or more non-retention flops to the retention flop list.

17. The computer-readable storage medium of claim 12, wherein one or more retention flops in the retention flop list are identified for modification to non-retention flops.

18. The computer-readable storage medium of claim 17, wherein modifying the retention flop list comprises removing one or more of the plurality of flops from the retention flop list.

19. The computer-readable storage medium of claim 17, wherein the accurate state comprises values of the plurality of flops being same before and after a power-sequence is performed.

20. The computer-readable storage medium of claim 19, the group of acts further comprising:

verifying the accurate state of the plurality of flops after a power-on delay has occurred for a first time period.

21. The computer-readable storage medium of claim 20, wherein the retention flop is identified by verifying the accurate state of the plurality of flops utilizing the retention list after the retention flop has been removed from the retention list.

22. The computer-readable storage medium of claim 20, further comprising:

increasing the duration of the first time period responsive to receiving an input from a user indicating the accurate state of the first plurality of flops should be verified after a longer power-on delay.