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Power aware retention flop list analysis and modification

  • US 9,104,824 B1
  • Filed: 04/30/2013
  • Issued: 08/11/2015
  • Est. Priority Date: 04/30/2013
  • Status: Expired due to Fees
First Claim
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1. A computer implemented method for retention flop list analysis, the method comprising:

  • receiving a first register transfer level (RTL) circuit model of a circuit design, the first RTL circuit model including a plurality of flops;

    receiving a power intent description of the circuit design, the power intent description including a retention flop list for a power domain;

    analyzing the first RTL circuit model and the power intent description to identify a retention flop of the plurality of flops for modification; and

    enhancing functionality of the plurality of flops by verifying the plurality of flops and performing a propagation analysis using a retention flop analysis mechanism that is coupled with at least one processor of a computing system and determines whether a conversion between the retention flop and a non-retention flop is to be performed based in part or in whole upon state information in the power domain and further by performing the conversion that has been determined to be performed while reducing a number of nets to be analyzed by the retention flop analysis mechanism coupled with the at least one processor in the analysis.

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