Methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic design

• US 9,104,830 B1
• Filed: 06/28/2013
• Issued: 08/11/2015
• Est. Priority Date: 06/28/2013
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Salowe, Jeffrey, Raj, Satish
• Primary Examiner(s): Whitmore, Stacy
• Assistant Examiner(s): Dimyan, Magid
• Application Number:
  US13/931,627
• Time in Patent Office: 774 Days
• Field of Search: 716/126, 716/129, 716/130
• US Class Current: 1/1
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 30/18 Network design, e.g. design based on topological or interconnect aspects of utility systems, piping, heating ventilation air conditioning [HVAC] or cabling circuit design at the physical level G06F30/39; network planning tools for wireless communication networks H04W16/18
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed are methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic design in one or more embodiments. One aspect tessellates an area on a layer of an electronic design that is subject to one or more track pattern requirements and dynamically maintains the tessellation structure from the tessellation process for early stages of the design process such as floorplanning, placement, or routing. Another aspect identifies or creates multiple strips or multiple regions for an area on a layer of an electronic design and assigns or associates a track pattern or a track pattern group to each of the multiple strips or multiple regions. In this latter aspect, a track pattern or a track pattern group is no longer required to apply to the entire layer.

Claims

1. A computer implemented method for implementing an electronic design with track patterns, comprising:

using a computing system having at least one processor or at least one processor core to perform a process, the process comprising;

identifying an area on a layer of an electronic design;

a tessellation mechanism coupled to the at least one processor or the at least one processor core of the computing system and identifying or creating multiple sub-areas for the area; and

automatically associating a track pattern or a track pattern group with a sub-area of the multiple sub-areas, wherein the track pattern or track pattern group comprises one or more routing tracks that are associated with one or more widths of circuit component designs implemented along at least one routing track of the one or more routing tracks.

2. The computer implemented method of claim 1, the act of identifying or creating multiple sub-areas further comprising:

determining whether the area has already been tessellated, wherein at least one sub-area of the multiple sub-areas comprises a strip or a region that is obtained from a tessellation process.

3. The computer implemented method of claim 1, the process further comprising:

maintaining a tessellation structure for the area; and

updating the tessellation structure during implementation of at least the area in the electronic design.

4. The computer implemented method of claim 1, the act of identifying or creating the multiple sub-areas for the area further comprising:

identifying a first strip or region from an existing tessellation structure;

tessellating the first strip or region into multiple first regions based at least in part on a set of criteria in a second direction that is different from a first direction that is used to form the first strip or region in the area; and

updating the existing tessellation structure with the multiple first regions.

5. The computer implemented method of claim 1, the act of identifying or creating the multiple sub-areas for the area further comprising:

identifying or determining whether there is an existing circuit feature in a first strip or region;

identifying or determining one or more characteristics of the existing circuit feature; and

incorporating the one or more characteristics of the existing circuit feature in a set of criteria for identifying or creating the multiple sub-areas.

6. The computer implemented method of claim 1, the act of identifying or creating the multiple sub-areas for the area further comprising:

identifying or determining a first adjacent area that is within a first distance from the area on the layer;

identifying or determining one or more first characteristics associated with the first adjacent area; and

incorporating the one or more first characteristics associated with the first adjacent area in a set of criteria for identifying or creating the multiple sub-areas.

7. The computer implemented method of claim 1, wherein the adjacent area is situated on a same layer on which the area is situated or on a different layer.

8. The computer implemented method of claim 1, the act of identifying or creating the multiple sub-areas for the area further comprising:

identifying one or more characteristics related to the electronic design; and

tessellating the area or the layer into one or more strips in a first direction based at least in part upon the one or more characteristics.

9. The computer implemented method of claim 8, the act of identifying or creating the multiple sub-areas for the area further comprising:

identifying a set of factors related to tessellation in a second direction;

tessellating a strip in the one or more strips in the second direction to form multiple second regions based at least in part on the set of factors; and

updating the existing tessellation structure with the multiple second regions.

10. A system for implementing an electronic design with track patterns, comprising:

a computing system having at least one processor or at least one processor core that is to;

identify an area on a layer of an electronic design;

identify or create, at a tessellation mechanism coupled to the at least one processor or the at least one processor core of the computing system, multiple sub-areas for the area; and

automatically associate a track pattern or a track pattern group with a sub-area of the multiple sub-areas, wherein the track pattern or track pattern group comprises one or more routing tracks that are associated with one or more widths of circuit component designs implemented along at least one routing track of the one or more routing tracks.

11. The system of claim 10, in which the at least one processor or at least one processor core that is to identify or create the multiple sub-areas is further to:

determine whether the area has already been tessellated, wherein at least one sub-area of the multiple sub-areas comprises a strip or a region that is obtained from a tessellation process.

12. The system of claim 10, in which the at least one processor or at least one processor core that is to identify or create the multiple sub-areas for the area is further to execute one or more sets of instructions of a plurality of sets of instructions to identify or create the multiple sub-areas for the area, wherein:

a first set of instructions of the plurality of sets of instructions comprises a first sequence of instructions which, when executed by the at least one processor, causes the at least one processor to;

identify a first strip or region from an existing tessellation structure;

tessellate the first strip or region into multiple first regions based at least in part on a set of criteria in a second direction that is different from a first direction that is used to form the first strip or region in the area; and

update the existing tessellation structure with the multiple first regions; and

a second set of instructions of the plurality of sets of instructions comprises a first sequence of instructions which, when executed by the at least one processor, causes the at least one processor to;

identify or determine whether there is an existing circuit feature in the first strip or region;

identify or determine one or more characteristics of the existing circuit feature; and

incorporate the one or more characteristics of the existing circuit feature in the set of criteria.

13. The system of claim 10, in which the at least one processor or at least one processor core that is to identify or create the multiple sub-areas for the area is further to execute one or more sets of instructions of a plurality of sets of instructions to identify or create the multiple sub-areas for the area, wherein:

a third set of instructions of the plurality of sets of instructions comprises a first sequence of instructions which, when executed by the at least one processor, causes the at least one processor to;

identify or determine a first adjacent area that is within a distance from the area on the layer;

identify or determine one or more characteristics associated with the first adjacent area; and

incorporate the one or more characteristics associated with the first adjacent area in a set of criteria; and

a fourth set of instructions of the plurality of sets of instructions comprises a first sequence of instructions which, when executed by the at least one processor, causes the at least one processor to;

identify or determine a first adjacent layer;

identify or determine one or more characteristics associated with the first adjacent layer; and

incorporate the one or more characteristics associated with the first adjacent layer in the set of criteria.

14. The system of claim 10, in which the at least one processor or at least one processor core that is to identify or create the multiple sub-areas for the area is further to execute one or more sets of instructions of a plurality of sets of instructions to identify or create the multiple sub-areas for the area, wherein:

identify one or more characteristics related to the electronic design; and

tessellate the area or the layer into one or more strips in a first direction based at least in part upon the one or more characteristics, wherein the at least one processor or at least one processor core that is to identify or create the multiple sub-areas for the area is further to;

identify a set of factors related to tessellation in a second direction;

tessellate a strip in the one or more strips in the second direction to form multiple second regions based at least in part on the set of factors; and

update the existing tessellation structure with the multiple second regions.

15. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a method for implementing an electronic design with track patterns, the method comprising:

using at least one processor or at least one processor core to perform a process the process comprising;

identifying an area on a layer of an electronic design;

a tessellation mechanism coupled to the at least one processor or the at least one processor core of the computing system and identifying or creating multiple sub-areas for the area; and

automatically associating a track pattern or a track pattern group with a sub-area of the multiple sub-areas, wherein the track pattern or track pattern group comprises one or more routing tracks that are associated with one or more widths of circuit component designs implemented along at least one routing track of the one or more routing tracks.

16. The article of manufacture of claim 15, the act of identifying or creating multiple sub-areas further comprising:

determining whether the area has already been tessellated, wherein at least one sub-area of the multiple sub-areas comprises a strip or a region obtained from a tessellation process;

maintaining a tessellation structure for the area; and

updating the tessellation structure during implementation of at least the area in the electronic design.

17. The article of manufacture of claim 15, the act of identifying or creating the multiple sub-areas for the area further comprising:

performing one or more sub-processes of a plurality of sub-processes, wherein

a first sub-process of the plurality of sub-processes comprises;

identifying a first strip or region from an existing tessellation structure;

tessellating the first strip or region into multiple first regions based at least in part on a set of criteria in a second direction that is different from a first direction that is used to form the first strip or region in the area; and

updating the existing tessellation structure with the multiple first regions; and

a second sub-process of the plurality of sub-processes comprises;

identifying or determining whether there is an existing circuit feature in the first strip or region;

identifying or determining one or more characteristics of the existing circuit feature; and

incorporating the one or more characteristics of the existing circuit feature in the set of criteria.

18. The article of manufacture of claim 15, the act of identifying or creating the multiple sub-areas for the area further comprising:

performing one or more sub-processes of a plurality of sub-processes to identify or create the multiple sub-areas, wherein

the third sub-process of the plurality of sub-processes comprises;

identifying or determining a first adjacent area that is within a distance from the area on the layer;

identifying or determining one or more characteristics associated with the first adjacent area; and

incorporating the one or more characteristics associated with the first adjacent area in a set of criteria; and

a fourth sub-process of the plurality of sub-processes comprises;

identifying or determining a first adjacent layer;

identifying or determining one or more characteristics associated with the first adjacent layer; and

incorporating the one or more characteristics associated with the first adjacent layer in the set of criteria.

19. The article of manufacture of claim 15, the act of identifying or creating the multiple sub-areas for the area further comprising:

performing a fifth sub-process of a plurality of sub-processes, wherein the fourth sub-process of the plurality of sub-processes comprises;

Identifying one or more characteristics related to the electronic design; and

tessellating the area or the layer into one or more strips in a first direction based at least in part upon the one or more characteristics.

20. The article of manufacture of claim 19, the act of identifying or creating the multiple sub-areas for the area further comprising:

identifying a set of factors related to tessellation in a second direction;

tessellating a strip in the one or more strips in the second direction to form multiple second regions based at least in part on the set of factors; and

updating the existing tessellation structure with the multiple second regions.