Systems and methods for single cell product path delay analysis

• US 9,104,834 B2
• Filed: 10/15/2014
• Issued: 08/11/2015
• Est. Priority Date: 01/07/2013
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Bickford, Jeanne P., Habitz, Peter A., Iyengar, Vikram, Worth, Brian A., Xiong, Jinjun
• Primary Examiner(s): Memula, Suresh
• Application Number:
  US14/514,919
• Publication Number:
  US 20150033199A1
• Time in Patent Office: 300 Days
• Field of Search: 716/113
• US Class Current: 1/1
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Methods and systems for qualifying a single cell with product path delay analysis are provided. A method includes designing a product using a model from an initial test site. The method also includes creating performance path tests for one or more paths on the product. The method further includes measuring performance path parameters of the product. The method includes determining that the measured performance path parameters match predicted performance path parameters.

Claims

1. A method, comprising:

establishing a path selection to test;

determining a process corner for each chip;

measuring at least one of a path delay and a frequency of each chip;

comparing data sensitivities based on a regression analysis with timing sensitivities; and

adjusting a timing margin setting based on the comparison of the data sensitivities and the timing sensitivities.

2. The method of claim 1, wherein path selection criteria to select the path to test comprises timing sensitivities of device components and path properties.

3. The method of claim 1, wherein the determining a process corner for each chip comprises determining a value of a parameter setting for each chip to be tested.

4. The method of claim 1, wherein qualification criteria of a selected path comprises at least one of voltages across an allowed operation range and temperatures across an allowed operation range.

5. The method of claim 1, wherein a selected path to be tested can be compared to one or more other paths to determine which device sensitivities occur on the selected path.

6. The method of claim 1, further comprising marginalizing data sensitivities that exceed a predetermined threshold of the timing sensitivities.

7. The method of claim 1, further comprising monitoring a timing sensitivity delta of the timing sensitivities, such that a timing methodology does not damage special paths.

8. The method of claim 1, wherein the timing margin setting is adjusted by updating at least one of processes for processing each chip, timing input and spice models.

9. A computer system for qualifying a performance path, the system comprising:

a CPU, a computer readable memory and a computer readable storage media;

first program instructions to create performance path tests for one or more paths on a product;

second program instructions to measure performance path parameters of the product;

third program instructions to determine that the measured performance path parameters match predicted performance path parameters; and

fourth program instructions to adjust a timing margin setting when the measured performance path parameters do not match the predicted performance path parameters,

wherein the first, second, third, and fourth program instructions are stored on the computer readable storage media for execution by the CPU via the computer readable memory.

10. The computer system of claim 9, wherein the creating the performance path tests comprises determining at least one of a path delay and a frequency of a selected path as a function of a process window sigma for the at least one of a path delay and a frequency.

11. The computer system of claim 10, wherein the determining that the measured performance path parameters match predicted performance path parameters comprises:

conducting a regression analysis;

inputting identified sensitivity input into a canonical model; and

comparing the regression analysis with a timing analysis.

12. The computer system of claim 11, further comprising fifth program instructions to marginalize data sensitivities that exceed a predetermined threshold of timing sensitivities of the one or more paths.

13. The computer system of claim 9, wherein the fourth program instructions adjust the timing margin setting by updating at least one of processes for processing the product, timing input and spice models.

14. A computer system for qualifying a performance path, the system comprising:

a CPU, a computer readable memory and a computer readable storage media;

first program instructions to establish a path selection to test;

first program instructions to determine a process corner for each chip;

first program instructions to measure at least one of a path delay and a frequency of each chip;

first program instructions to compare data sensitivities based on a regression analysis with timing sensitivities; and

first program instructions to adjust a timing margin setting based on the comparison of the data sensitivities and the timing sensitivities.

15. The computer system of claim 14, wherein path selection criteria to select the path to test comprises timing sensitivities of device components and path properties.

16. The computer system of claim 14, wherein:

the determining a process corner for each chip comprises determining a value of a parameter setting for each chip to be tested; and

further comprising;

qualification criteria of a selected path comprises at least one of voltages across an allowed operation range and temperatures across an allowed operation range;

a selected path to be tested can be compared to one or more other paths to determine which device sensitivities occur on the selected path; and

marginalizing data sensitivities that exceed a predetermined threshold of the timing sensitivities.

17. The computer system of claim 14, wherein the first program instructions to adjust the timing margin update at least one of processes for processing each chip, timing input and spice models.