Systems and methods for determining effective capacitance to facilitate a timing analysis

• US 9,104,835 B2
• Filed: 12/08/2014
• Issued: 08/11/2015
• Est. Priority Date: 10/11/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeh, Chao-Yang, Yeh, Cheng-Hung, Huang, Chi-Ting
• Primary Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US14/562,793
• Publication Number:
  US 20150154343A1
• Time in Patent Office: 246 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method for timing analysis includes using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and a second ILV or a device, as a function of at least different frequency values. The impedance profile includes a plurality of impedance values corresponding to respective frequency values. An effective capacitance value corresponding to each respective impedance value is determined. At least one table is provided with respective impedance values and respective effective capacitance values for each respective frequency value. An RC extraction of a design layout of an ILV circuit is conducted using the populated table and based on determined effective capacitance values.

Claims

1. A method for timing analysis using a processor, comprising:

using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and one of the group consisting of a second ILV and a device as a function of at least different frequency values, wherein the impedance profile includes a plurality of impedance values corresponding to respective frequency values;

determining an effective capacitance value corresponding to each respective impedance value;

providing at least one table with respective impedance values and respective effective capacitance values for each respective frequency value; and

conducting an RC extraction of a design layout of an ILV circuit using the populated table and based on determined effective capacitance values therein.

2. The method of claim 1, wherein using the processor to determine an impedance profile between the first ILV and the second ILV comprises determining an impedance profile between the first and second ILVs as a function of different spacing values.

3. The method of claim 2, wherein determining an effective capacitance value comprises determining an effective capacitance value at each of the different spacing values.

4. The method of claim 1, wherein using the processor to determine the impedance profile of the coupling between the first ILV and the device includes determining a coupling between the first ILV and a transistor.

5. The method of claim 4, wherein the model has each of the at least two ILVs coupled to ground by a respective capacitor having the capacitance values that are approximately half of each of the effective capacitance values.

6. The method of claim 5, wherein the model excludes a coupling noise between the at least two ILVs.

7. The method of claim 6, further comprising performing a full chip static timing analysis using the RC network.

8. The method of claim 1, wherein the effective capacitance values vary based on frequency and based on locations of ILVs within an IC.

9. The method of claim 1, wherein conducting an RC extraction comprises conducting an RC extraction of the design layout using respectively different effective capacitance values for ILVs assigned to different signal groups.

10. The method of claim 1, the RC extraction uses respectively different effective capacitance values for ILVs located in different regions of an IC having respectively different TSV densities.

11. A system comprising:

a non-transient machine readable storage medium storing a model that is representative of a coupling between at least two inter-level vias (“

ILVs”

) generated by an electronic design automation (“

EDA”

) tool; and

an RC tool and a static timing analysis (“

STA”

) tool within the EDA tool such that the EDA tool is configured to;

determine an impedance profile between the at least two ILVs as a function of at least different frequency values by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective frequency values;

determine an effective capacitance value corresponding to each respective impedance value;

conduct an RC extraction of a design layout of an ILV circuit based on respective effective capacitance values to generate an RC network, where the effective capacitance values vary based on frequency and based on locations of ILVs within an IC; and

use the RC network for a timing analysis.

12. The system of claim 11, wherein the EDA tool is configured to determine the effective capacitance value at each of the different frequency values and different spacing values.

13. The system of claim 11, wherein the EDA tool is configured to determine the impedance profile between the at least two ILVs as a function of different spacing values.

14. The system of claim 13, wherein the EDA tool is configured to determine the effective capacitance value at each of the different spacing values.

15. The system of claim 11, wherein the EDA tool is configured to conduct the RC extraction of the design layout using predefined capacitance values that are approximately half of each of the effective capacitance values.

16. The system of claim 11, wherein the EDA tool is configured to conduct the RC extraction of the design layout using respectively different effective capacitance values for ILVs located in different regions of an IC.

17. At least one non-transitory computer-readable storage medium having computer-executable instructions embodied thereon, wherein, when executed by at least one processor, the computer-executable instructions cause the at least one processor to:

provide a model that is representative of a coupling between at least two inter-level vias (“

ILVs”

);

determine an impedance profile between the at least two ILVs as a function of at least different frequency values by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective frequency values;

determine an effective capacitance value corresponding to each respective impedance value;

store at least one table with respective impedance values and respective effective capacitance values for each respective frequency value, the stored impedance values and effective capacitance values accessible by the at least one processor; and

conduct an RC extraction of a design layout of an ILV circuit based on the effective capacitance values in the table to generate an RC network.

18. The at least one non-transitory computer-readable storage medium of claim 17, wherein the computer-executable instructions cause the at least one processor to determine the impedance profile between the at least two ILVs as a function of different frequency values and different spacing values.

19. The at least one non-transitory computer-readable storage medium of claim 18, wherein the computer-executable instructions cause the at least one processor to determine the effective capacitance value at each of the different frequency values and different spacing values.

20. The at least one non-transitory computer-readable storage medium of claim 17, wherein the computer-executable instructions further cause the at least one processor to use the RC network for a timing analysis.