Memory devices and methods of operating the same

• US 9,105,320 B2
• Filed: 10/16/2013
• Issued: 08/11/2015
• Est. Priority Date: 10/16/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Schubert, Martin F., Sills, Scott E.
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US14/055,643
• Publication Number:
  US 20150103613A1
• Time in Patent Office: 664 Days
• Field of Search: 365/231, 365/148, 365/163
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/78 Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

The present disclosure includes memory devices and methods of operating the same. One such device includes an array of groups of memory cells, a group selector configured to select a particular group of memory cells from within the array, and a cell selector configured to select a particular memory cell from within the selected particular group of memory cells.

Claims

1. A device, comprising:

an array of groups of memory cells;

a group selector configured to select a particular group of memory cells from within the array,

wherein remaining groups of memory cells within the array include partially-selected memory cells and suppressed non-selected memory cells; and

a cell selector configured to select a particular memory cell from within the selected particular group of memory cells.

2. The device of claim 1, wherein the groups of memory cells comprise a stack of memory cells.

3. The device of claim 2, wherein the stack of memory cells comprises a vertical stack of non-volatile memory cells.

4. The device of claim 1, wherein the group selector comprises a three-terminal access device.

5. The device of claim 1 wherein the cell selector comprises a two-terminal access device.

6. The device of claim 5, wherein the two-terminal access device comprises a two-terminal ovonic threshold switch (OTS).

7. The device of claim 1, wherein the array comprises a two-dimensional array.

8. The device of claim 1, wherein the array comprises a three-dimensional array.

9. A device, comprising:

a three-terminal group selector to select a group of memory cells from within an array of memory cells, wherein remaining groups of memory cells within the array include partially-selected memory cells and suppressed non-selected memory cells, and wherein the three-terminal group selector comprises;

a first terminal coupled to a first conductive line;

a second terminal coupled to a second conductive line;

a third terminal is coupled to the group of memory cells; and

a cell selector to select a memory cell from within the group of memory cells.

10. The device of claim 9, wherein the group of memory cells comprises a vertical stack of RRAM elements.

11. The device of claim 9, wherein the first conductive line comprises an access line.

12. The device of claim 9, wherein the second conductive line comprises a data line.

13. The device of claim 9, wherein the three-terminal group selector comprises a transistor.

14. A device, comprising:

an array of groups of memory cells, wherein each group of memory cells comprises a stack of resistance variable materials;

a number of three-terminal group selectors configured to select particular groups of memory cells from within the array,

wherein remaining groups of memory cells within the array include partially-selected memory cells and suppressed non-selected memory cells; and

wherein at least a first memory cell in a first group of the array of groups of memory cells and a second cell in a second group of the array of groups of memory cells share a source line within the array; and

a number of two-terminal select devices configured to select a particular memory cell from within the selected particular group of memory cells.

15. The device of claim 14, wherein the shared source line comprises a shared source plane.

16. An array of memory cells, comprising:

a first group of memory cells selectable by a first group selector;

a memory cell within the first group of memory cells selectable by a first cell selector;

a second group of memory cells selectable by a second group selector and adjacent to the first group of memory cells;

a memory cell within the second group of memory cells selectable by a second cell selector;

wherein the memory cell within the first group of memory cells and the memory cell within the second group of memory cells share a source line of the array of memory cells;

a third group of memory cells within the array comprising partially-selected memory cells; and

a fourth group of memory cells within the array comprising suppressed non-selected memory cells.

17. The array of claim 16, wherein the first group selector comprises:

a first terminal coupled to the first group of memory cells;

a second terminal coupled to a first conductive line of the array; and

a third terminal coupled to a second conductive line of the array.

18. The array of claim 17, wherein the first conductive line comprises an access line, the second conductive line comprises a data line, and the first conductive line is substantially parallel to the second conductive line.

19. The array of claim 17, wherein the first conductive line comprises an access line, the second conductive line comprises a data line, and the first conductive line is substantially perpendicular to the second conductive line.

20. The array of claim 17, wherein the first conductive line comprises an access line, the second conductive line comprises a data line, and the first conductive line is neither parallel nor perpendicular to the second conductive line.

21. The array of claim 17, further comprising a third conductive line coupled to the memory cells of the array, wherein the first conductive line comprises an access line, the second conductive line comprises a data line, and the third conductive line comprises a source line,

wherein the third conductive line is perpendicular to at least one of the first conductive line and the second conductive line.

22. The array of claim 16, wherein the first group of memory cells and the second group of memory cells comprise groups of non-volatile memory cells.

23. The array of claim 16, wherein the memory cell within the first group of memory cells is in series with the first cell selector and the memory cell within the second group of memory cells is in series with the second cell selector.

24. The array of claim 16, wherein the first and second cell selectors comprise non-ohmic devices (NOD).

25. A method for operating a device, comprising:

applying a first bias to a group selector in an array of memory cells to activate the group selector;

selecting a first group of memory cells from within the array of memory cells using the group selector;

applying a second bias between a data line and a source line in the array of memory cells to select a particular memory cell from within the selected first group of memory cells;

partially selecting a second group of memory cells from within the array of memory cells; and

suppressing a third, non-selected group of memory cells from within the array of memory cells.