Memory cell array operated with multiple operation voltage

• US 9,105,355 B2
• Filed: 07/04/2013
• Issued: 08/11/2015
• Est. Priority Date: 07/04/2013
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Hsin-Wen
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US13/935,487
• Publication Number:
  US 20150009749A1
• Time in Patent Office: 768 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A memory cell array includes a bit line, a complementary bit line, a first operation voltage supply circuit, a second operation voltage supply circuit, a first memory cell and a second memory cell. The first operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a first operation voltage. The second operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a second operation voltage. The first memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the first operation voltage. The second memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the second operation voltage. The first and second memory cells are located in a same column in the memory cell array.

Claims

1. A memory cell array, comprising:

a bit line;

a complementary bit line;

a first operation voltage supply circuit, electrically coupled to the bit line and the complementary bit line, configured to provide a first operation voltage;

a second operation voltage supply circuit, electrically coupled to the bit line and the complementary bit line, configured to provide a second operation voltage;

a first memory cell, electrically coupled to the bit line and the complementary bit line, configured to receive the first operation voltage; and

a second memory cell, electrically coupled to the bit line and the complementary bit line, configured to receive the second operation voltage;

wherein the first and second memory cells are located in a same column in the memory cell array;

wherein the first and second operation voltage supply circuits both comprise;

a node for generating the first or the second operation voltage;

a first N-type transistor configured to have one source/drain thereof electrically coupled to a first source voltage and another source/drain thereof electrically coupled to the node;

a second N-type transistor configured to have one source/drain thereof electrically coupled to the first source voltage and another source/drain thereof electrically coupled to the node;

a first P-type transistor configured to have one source/drain thereof electrically coupled to the node and a gate thereof electrically coupled to a gate of the second N-type transistor;

a second P-type transistor configured to have one source/drain thereof electrically coupled to another source/drain of the first P-type transistor, another source/drain thereof electrically coupled to the first source voltage, and a gate thereof electrically coupled to a gate of the first N-type transistor;

a first inverter configured to have an input terminal thereof electrically coupled to the bit line and an output terminal thereof electrically coupled to a gate of the second P-type transistor; and

a second inverter configured to have an input terminal thereof electrically coupled to the complementary bit line and an output terminal thereof electrically coupled to a gate of the first P-type transistor;

wherein the first operation voltage or the second operation voltage at the node is equal to or smaller than the first source voltage.

2. The memory cell array according to claim 1, wherein both of the first and second N-type transistors are a low-threshold-voltage transistor.

3. The memory cell array according to claim 1, wherein both of the first and second N-type transistors are a high-threshold-voltage transistor.

4. The memory cell array according to claim 1, wherein both of the first and second N-type transistors are a general-threshold-voltage transistor.

5. The memory cell array according to claim 1, further comprising:

at least a write word line electrically coupled to the first memory cell or the second memory cell.