Package-on-package assembly with wire bond vias

• US 9,105,483 B2
• Filed: 02/24/2012
• Issued: 08/11/2015
• Est. Priority Date: 10/17/2011
• Status: Active Grant

• Current Assignee: Invensas LLC (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Chau, Ellis, Co, Reynaldo, Alatorre, Roseann, Damberg, Philip, Wang, Wei-Shun, Yang, Se Young
• Primary Examiner(s): Sun, Yu-Hsi D
• Application Number:
  US13/404,408
• Publication Number:
  US 20130093087A1
• Time in Patent Office: 1,264 Days
• Field of Search: 257/696, 257/697, 257/693, 257/E23.023, 257/E23.024, 257/784, 438/617
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/4554 Coating
• CPC Class Codes: H01L 2224/45565 Single coating layer
• CPC Class Codes: H01L 2224/45664 Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 : the bodies being stacked
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 : Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48245 : the item being metallic
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48997 : Reinforcing structures
• CPC Class Codes: H01L 2224/49171 : Fan-out arrangements
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/78301 : Capillary
• CPC Class Codes: H01L 2224/851 : the connector being supplied to the parts to be connected in the bonding apparatus
• CPC Class Codes: H01L 2224/8518 : Translational movements
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/85951 : Forming additional members, e.g. for reinforcing
• CPC Class Codes: H01L 2224/85986 : Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06558 : the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06565 : the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1029 : the support being a lead frame
• CPC Class Codes: H01L 2225/1052 : Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 : Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 2225/1094 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3677 : Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/4334 : Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49517 : Additional leads
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/43 : Manufacturing methods
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/78 : Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1715 : Shape
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/20751 : larger or equal to 10 microns less than 20 microns
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/20754 : larger or equal to 40 microns less than 50 microns
• CPC Class Codes: H01L 2924/20755 : larger or equal to 50 microns less than 60 microns
• CPC Class Codes: H01L 2924/20756 : larger or equal to 60 microns less than 70 microns
• CPC Class Codes: H01L 2924/20757 : larger or equal to 70 microns less than 80 microns
• CPC Class Codes: H01L 2924/20758 : larger or equal to 80 microns less than 90 microns
• CPC Class Codes: H01L 2924/20759 : larger or equal to 90 microns less than 100 microns
• CPC Class Codes: H01L 2924/2076 : equal to or larger than 100 microns
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H05K 2201/10515 : Stacked components
• CPC Class Codes: H05K 2201/1053 : Mounted components directly electrically connected to each other, i.e. not via the PCB
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: Y10T 29/49149 : by metal fusion bonding
• CPC Class Codes: Y10T 29/49151 : by deforming or shaping

Abstract

A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 90° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds.

Claims

1. A microelectronic package comprising:

a substrate having a first region and a second region, the substrate having a first surface and a second surface remote from the first surface;

at least one microelectronic element overlying the first surface within the first region;

electrically conductive elements exposed at at least one of the first surface and the second surface of the substrate within the second region, at least some of the conductive elements being electrically connected to the at least one microelectronic element;

wire bonds, each defining a base joined to a respective one of the conductive elements, and each wire bond having a second portion extending in a direction of a length of the respective wire bond away from the respective base, the second portion extending upwardly relative to the at least one surface of the substrate at an angle between 25° and

90°

, the wire bonds further having ends remote from the substrate and remote from the bases, wherein at least one of the wire bonds has an axis defined between the end and the base thereof and coincident with a side surface thereof, wherein the at least one of the wire bonds in its entirety is positioned on one side of the axis thereof, wherein the end of the at least one of the wire bonds is defined on a tip that is tapered in at least one direction extending beyond a cylindrical portion of the at least one of the wire bonds immediately adjacent the tip but not in a direction opposite to the at least one direction extending beyond the cylindrical portion, in which the tip has a centroid that is offset in a radial direction from an axis of the cylindrical portion of the wire bond; and

a dielectric encapsulation layer extending from at least one of the first or second surfaces and covering portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, the encapsulation layer overlying at least the second region of the substrate, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends.

2. The microelectronic package as set forth in claim 1, wherein the angle is between 45°

and 90°

.

3. The microelectronic package as set forth in claim 1, wherein a first one of the wire bonds is adapted for carrying a first signal electric potential and a second one of the wire bonds is adapted for simultaneously carrying a second signal electric potential different from the first signal electric potential.

4. The microelectronic package as set forth in claim 1, wherein each wire bond has an edge surface extending between the base and at least the end thereof, wherein the unencapsulated portions of the wire bonds are defined by the ends of the wire bonds and portions of edge surfaces adjacent the ends that are uncovered by the encapsulation layer.

5. The microelectronic package as set forth in claim 1, wherein the tapered tips on which at least some of the ends are defined are tapered in multiple directions.

6. The microelectronic package as set forth in claim 1, wherein the tips have bonding tool marks thereon.

7. The microelectronic package as set forth in claim 1, further comprising an oxidation protection layer contacting at least some of the unencapsulated portions of the wire bonds.

8. The microelectronic package as set forth in claim 1, wherein at least some of the wire bonds have a core of a primary metal and a metallic finish including a second metal different from the primary metal overlying the primary metal.

9. The microelectronic package as set forth in claim 8, wherein the metallic finish includes palladium.

10. The microelectronic package as set forth in claim 1, wherein at least some of the wire bonds are formed of a primary metal, with a layer of nickel overlying the primary metal and a layer of gold or silver overlying the layer of nickel.

11. The microelectronic package as set forth in claim 10, wherein the primary metal is one of gold or copper.

12. The microelectronic package as set forth in claim 1, wherein the conductive elements are first conductive elements, the microelectronic package further comprising a plurality of second conductive elements electrically connected to the unencapsulated portions of the wire bonds, wherein the second conductive elements do not contact the first conductive elements.

13. The microelectronic package as set forth in claim 12, wherein the second conductive elements include a monolithic metal layer consisting essentially of a single metal.

14. The microelectronic package as set forth in claim 13, wherein the single metal is one of:

nickel, gold, copper, palladium or silver.

15. The microelectronic package as set forth in claim 12, wherein the second conductive elements include a conductive paste contacting the unencapsulated portions of the wire bonds.

16. The microelectronic package as set forth in claim 1, wherein an end of at least one of the wire bonds is displaced in a direction parallel to the first surface of the substrate from its base by at least a distance equal to one of:

a minimum pitch between adjacent conductive elements of the plurality of conductive elements, and 100 microns.

17. The microelectronic package as set forth in claim 16, wherein at least one of the wire bonds includes at least one bend between the base thereof and the unencapsulated portion thereof.

18. The microelectronic package as set forth in claim 17, wherein the bend of the at least one wire bond is remote from the base thereof and remote from the unencapsulated portion thereof.

19. The microelectronic package as set forth in claim 17, wherein the unencapsulated portion of the at least one wire bond overlies a major surface of the microelectronic element.

20. The microelectronic package as set forth in claim 1, wherein the bases of the wire bonds are disposed at positions in a first pattern having a first minimum pitch between respective adjacent bases of the plurality of wire bonds, and the unencapsulated portions of the wire bonds are disposed at positions in a second pattern having a second minimum pitch between respective adjacent unencapsulated portions of wire bonds of the plurality of wire bonds, the second minimum pitch being greater than the first pitch.

21. The microelectronic package as set forth in claim 1, wherein the at least one microelectronic element includes first and second microelectronic elements overlying the first surface within the first region, and wherein at least some of the conductive elements are connected with the first microelectronic element, wherein at least some conductive elements are connected with the second microelectronic element, and wherein the first microelectronic element and the second microelectronic elements are electrically connected with one another within the microelectronic package.

22. The microelectronic package as set forth in claim 1, wherein at least one of the first conductive elements has at least two wire bonds joined thereto.

23. A microelectronic assembly, comprising:

a first microelectronic package according to claim 1

a second microelectronic package including a second microelectronic element and terminals electrically connected to the second microelectronic element and exposed at a surface of the second microelectronic package; and

a plurality of conductive protrusions electrically connecting at least some of the unencapsulated portions of the wire bonds with respective ones of the terminals.

24. The microelectronic assembly as set forth in claim 23, wherein the encapsulation layer of the first microelectronic package includes a major surface and an alignment surface sloping upwardly away from the major surface, at least one unencapsulated portion of the wire bond being positioned on the major surface and the alignment surface extending to a location proximate the major surface and proximate the at least one unencapsulated portion of the wire bond such that a conductive protrusion connecting the at least one unencapsulated portion of the wire bond contacts the alignment surface.

25. The microelectronic assembly as set forth in claim 23, further including an underfill disposed within a space defined between confronting surfaces of the first microelectronic package and the second microelectronic package and between respective adjacent conductive protrusions of the plurality of conductive protrusions.

26. The microelectronic assembly as set forth in claim 1, wherein the wire bonds define edge surfaces having portions defined along the bases of the wire bonds such that the bases are bonded to the respective ones of the conductive elements with the edge surfaces extending along the conductive elements.

27. The microelectronic assembly as set forth in claim 26, wherein the second portions of the wire bonds extend upwardly relative to the at least one surface of the substrate at an angle between 25°

and 90°

relative to the bases.

28. The microelectronic assembly as set forth in claim 26, wherein the portions of the edge surfaces along the bases are wedge bonded or stitch bonded to the respective ones of the conductive elements.

29. A microelectronic package comprising:

a substrate having a first region and a second region, the substrate having a first surface and a second surface remote from the first surface;

at least one microelectronic element overlying the first surface within the first region;

electrically conductive elements exposed at at least one of the first surface and the second surface of the substrate within the second region, at least some of the conductive elements being electrically connected to the at least one microelectronic element;

wire bonds, each defining a base joined to a respective one of the conductive elements, and each wire bond having a second portion extending in a direction of a length of the respective wire bond away from the respective base, the second portion extending upwardly relative to the at least one surface of the substrate at an angle between 25° and

90°

, the wire bonds further having ends remote from the substrate and remote from the bases, wherein each of at least some of the wire bonds has an axis defined between the end and the base thereof and coincident with a side surface thereof, wherein the each of the at least some of the wire bonds in its entirety is positioned on one side of the axis thereof, wherein the ends of the at least some of the wire bonds are defined on tips that are tapered in at least one direction extending beyond cylindrical portions respectively of the at least some of the wire bonds immediately adjacent the tips but not in a direction opposite to the at least one direction extending beyond the cylindrical portions, in which the ends have bonding tool marks thereon; and

a dielectric encapsulation layer extending from at least one of the first or second surfaces and covering portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, the encapsulation layer overlying at least the second region of the substrate, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends.