Integrated circuit comprising on-chip resistors with plurality of first and second terminals coupled to the resistor body

• US 9,105,502 B2
• Filed: 06/04/2013
• Issued: 08/11/2015
• Est. Priority Date: 06/05/2012
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Zhang, Guowei, Verma, Purakh Raj, Khon, Cho
• Primary Examiner(s): Tran, Long K
• Assistant Examiner(s): Tran, Dzung
• Application Number:
  US13/910,077
• Publication Number:
  US 20130320497A1
• Time in Patent Office: 798 Days
• Field of Search: 257/538, 257/312, 257/592, 257/343, 257/48, 257/380, 438/758, 338/308
• US Class Current: 1/1
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 27/101 including resistors or capacitors only

Abstract

An integrated circuit (IC) is disclosed. The IC includes a substrate with a resistor region and a resistor body disposed on the resistor region. A plurality of first resistor contact strips and a plurality of second resistor contact strips are disposed on the resistor body along a first direction. Two adjacent first and second resistor contact strips are separated by a respective one of contact strip spaces. The IC includes a plurality of first terminals and a plurality of second terminals. Each of the first terminals is coupled to a respective one of the first resistor contact strips while each of the second terminals is coupled to a respective one of the second resistor contact strips. A set of the first terminal and the second terminal forms first and second terminals of an on-chip resistor.

Claims

1. An integrated circuit (IC), comprising:

a substrate with a resistor region, the resistor region includes an isolation region in the substrate;

a resistor body directly disposed on and contacts the isolation region;

a plurality of first and second contacts/vias formed on the resistor body, wherein a resistor portion of the resistor body between the first and second contacts/vias forms a resistor;

a terminal ILD layer disposed over the plurality of first and second contacts/vias; and

first and second terminal plates which are non-rectangular terminal plates disposed in the terminal ILD layer, wherein adjacent sides of the first and second terminal plates are separated by a space and adjacent sides of the first and second terminal plates are slanted and configured to encompass the same number of contacts/vias.

2. The IC of claim 1 comprising:

first and second alternating contact strips disposed on the resistor body along a first direction, wherein the first and second alternating contact strips serve as first and second resistor terminals;

contact strip space regions which comprise silicide blocks separating the first and second alternating contact strips; and

a separate dielectric layer disposed on the substrate, wherein the dielectric layer covers and contacts the substrate and the resistor body including the contact strips and contact strip space regions.

3. The IC of claim 2, wherein the contact strips comprise metal silicide contact strips.

4. The IC of claim 1, wherein the resistor body comprises polysilicon, Ta, or TaN.

5. The IC of claim 4, wherein the resistor body comprises heavily doped polysilicon.

6. The IC of claim 1, wherein an outer perimeter of the first and second terminal plates together has a size and shape similar to the resistor body.

7. The IC of claim 2, wherein the resistor body in the contact strip space region separating the first and second alternating contact strips forms a resistor.

8. The IC of claim 1, wherein the terminal plates are trapezoidal shaped terminal plates and are slanted at an angle following the direction of current flow of the resistor.

9. The IC of claim 2 comprising:

a plurality of first conductive lines disposed above a respective one of the first resistor terminals,

the plurality of first contacts/vias couple the respective one of the first resistor terminals to corresponding first conductive lines; and

a plurality of second conductive lines disposed above a respective one of the second resistor terminals,

the plurality of second contacts/vias couple the respective one of the second resistor terminals to corresponding second conductive lines.

10. The IC of claim 9, wherein:

the first terminal plate is coupled to the first conductive lines; and

the second terminal plate is coupled to the second conductive lines.

11. The IC of claim 10, wherein:

the first and second conductive lines are disposed on a first metal layer of the IC; and

the first and second terminal plates are disposed on a second metal layer of the IC.

12. The IC of claim 11, wherein the first metal layer is a lowest metal layer (M₁) of the IC and the second metal layer is a highest metal layer (Mx) of the IC, and x is an integer greater than 1.

13. The IC of claim 12, wherein one or more intermediate metal layers are disposed between M₁ and M_x, the one or more intermediate metal layers having a same pattern as that of the M_x.

14. The IC of claim 1, wherein the resistor is among a plurality of on-chip resistors that are coupled in parallel.

15. The IC of claim 1, wherein the on-chip resistor is disposed below a bond pad of the IC.

16. The IC of claim 10, wherein the non-rectangular terminal plates having adjacent sides which are slanted result in different first conductive lines having different amount of contacts/vias and different second conductive lines having different amounts of contacts/vias.

21. The IC of claim 1, wherein the plurality of first and second resistor terminals contacts the resistor body.

17. An integrated circuit (IC), comprising:

a substrate with a resistor region, the resistor region including an isolation region in the substrate;

a resistor body directly disposed on and contacts the isolation region;

a plurality of first contacts/vias coupled to the resistor body;

a plurality of second contacts/vias coupled to the resistor body, wherein a resistor portion of the resistor body between the first and second contacts/vias forms a resistor;

a terminal ILD layer disposed over the plurality of first and second contacts/vias; and

first and second terminal plates which are non-rectangular shaped terminal plates disposed in the terminal ILD layer, wherein adjacent sides of the first and second terminal plates are separated by a space and adjacent sides of the first and second terminal plates are slanted and configured to encompass the same number of contacts/vias.

18. The IC of claim 17, wherein the resistor body is a conductive metal comprising Ta, or TaN.

19. The IC of claim 17, wherein the portion of resistor body forming the resistor is below a silicide block.

20. The IC of claim 17, wherein an outer perimeter of the first and second terminal plates together has a size and shape similar to the resistor body.

22. The IC of claim 17 comprising:

first and second alternating contact strips disposed on the resistor body along a first direction;

contact strip spaces separating the first and second alternating contact strips; and

wherein the first and second alternating contact strips serve as first and second terminals of the resistor.

23. The IC of claim 17, wherein the plurality for first and second resistor terminals contacts the resistor body.