Method of fabricating a thin film transistor array substrate

• US 9,105,524 B2
• Filed: 11/13/2013
• Issued: 08/11/2015
• Est. Priority Date: 04/30/2013
• Status: Expired due to Fees

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Choi, Hee Dong
• Primary Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US14/079,184
• Publication Number:
  US 20140319526A1
• Time in Patent Office: 636 Days
• Field of Search: 257/98, 257/59, 257/72, 438/151, 438/128
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1237 with a different composition, shape, layout or thickness of the gate insulator in different devices
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin film transistor array substrate including a gate line and a data line formed on a substrate, the gate and data lines crossing each other; a gate insulation film formed between the gate and data lines; a gate electrode formed at an intersection of the gate and data lines; an active layer formed on the gate insulation film to overlap the gate electrode; an etch stop layer formed on the active layer to define a channel region of the active layer; and a source electrode and a drain electrode formed on the active layer to partially overlap the active layer. The etch stop layer is between the source and drain electrodes, and the source and drain electrodes are spaced apart from the etch stop layer.

Claims

1. A method of fabricating a thin film transistor array substrate, the method comprising:

forming a gate electrode on a substrate;

forming a gate insulation film on the substrate on the gate electrode;

forming an active layer on the gate insulation film;

forming an etch stop layer to define a channel region of the active layer;

sequentially forming a barrier layer and a metal layer on the gate insulation film, the active layer, and the etch stop layer; and

forming a source electrode and a drain electrode which are spaced apart from the etch stop layer,

wherein the etch stop layer is between the source and drain electrodes, and

the formation of the source and drain electrodes includes;

forming a barrier layer on the entire surface of the substrate provided with the etch stop layer;

forming a metal layer on the barrier layer;

forming a second source electrode layer and a second drain electrode layer by etching the metal layer; and

forming a first source electrode layer and a first drain electrode layer by dry-etching the barrier layer using the second source and drain electrodes as an etching mask, and

wherein the source electrode includes the first and second source electrode layers and the drain electrode includes the first and second drain electrode layers.

2. The method of claim 1, wherein the source and drain electrodes do not overlap the gate electrode.

3. The method of claim 1, wherein the formation of the etch stop layer includes:

sequentially stacking an active protection layer and a photoresist on the substrate above the active layer;

patterning the photoresist into a photoresist pattern on a partial region of the active protection layer overlapping the gate electrode, by performing a rear exposure for the photoresist using the gate electrode as a mask;

patterning the active protection layer into the etch stop layer by etching the active protection layer using the photoresist pattern as an etching mask; and

removing the photoresist pattern from the etch stop layer.

4. The method of claim 1, wherein the active layer is formed only in a region over the gate electrode.

5. The method of claim 1, wherein the source electrode is formed in a shape of U.

6. The method of claim 5, wherein both ends of the source electrode are arranged without overlapping the gate electrode.

7. The method of claim 5, wherein the source electrode is formed only in a region adjacent to the gate electrode.

8. The method of claim 1, wherein the second source and drain electrode layers are formed by wet-etching the metal layer.