Solid-state imaging device

• US 9,105,544 B2
• Filed: 12/20/2012
• Issued: 08/11/2015
• Est. Priority Date: 07/09/2010
• Status: Active Grant

• Current Assignee: Panasonic Intellectual Property Management Co., Ltd. (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Intellectual Property Management Co., Ltd. (Panasonic Holdings Corporation)
• Inventors: Matsunaga, Yoshiyuki
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US13/722,135
• Publication Number:
  US 20130113060A1
• Time in Patent Office: 964 Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14638 Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14665 Imagers using a photoconductor layer

Abstract

A solid-state imaging device including unit pixel cells, each having a photoelectric conversion film and a pixel electrode which are formed above a silicon substrate, an amplification transistor which is formed on the silicon substrate and outputs a voltage according to a potential of the pixel electrode, and a reset transistor which is formed on the silicon substrate and resets a potential of a gate electrode of the amplification transistor, the imaging device including a vertical signal line which is disposed correspondingly to a column of the unit pixel cells, and transmits a voltage of the unit pixel cells of the corresponding column, and a vertical scanning unit which selects a row of the unit pixel cells having a voltage to be outputted to the vertical signal line, wherein the vertical signal line is located below the pixel electrode of the unit pixel cells corresponding to the vertical signal line.

Claims

1. A solid-state imaging device comprising

a plurality of unit pixel cells arranged in a two-dimensional array, and

each of the pixel units cell including:

a photoelectric conversion film which is formed above a semiconductor substrate and photoelectrically converts an incident light;

a pixel electrode which is formed above the semiconductor substrate and is in contact with the photoelectric conversion film;

an amplification transistor which is formed on the semiconductor substrate, has a gate electrode connected to the pixel electrode, and outputs a signal voltage according to a potential of the pixel electrode;

a reset transistor which is formed on the semiconductor substrate, and resets a potential of the gate electrode of the amplification transistor;

a via contact for connecting the gate electrode of the amplification transistor to the pixel electrode; and

connection wiring for connecting the reset transistor to the pixel electrode and the gate electrode of the amplification transistor,

the reset transistor being connected to the pixel electrode via the via contact and the connection wiring, and

the reset transistor being located below the pixel electrode and closer to an edge of the pixel electrode than a connection point between the via contact and the pixel electrode,

the solid-state imaging device further comprising;

a vertical signal line which is provided correspondingly to a column of the unit pixel cells, and transmits a signal voltage of the unit pixel cells of the corresponding column; and

a row selection unit configured to select a row of the unit pixel cells having a signal voltage to be outputted to the vertical signal line.

2. The solid-state imaging device according to claim 1, wherein the vertical signal line includes wiring in a wiring layer other than a wiring layer in an uppermost region of a multi-layered wiring layer provided between (i) the amplification transistor and the reset transistor, and (ii) the pixel electrode.

3. The solid-state imaging device according to claim 2, wherein the vertical signal line includes wiring in a lowermost region of the multi-layered wiring layer provided between (i) the amplification transistor and the reset transistor, and (ii) the pixel electrode.

4. The solid-state imaging device according to claim 3, wherein the connection wiring includes wiring in a wiring layer in the lowermost region of the multi-layered wiring layer provided between (i) the gate electrode of the amplification transistor and a gate electrode of the reset transistor, and (ii) the pixel electrode.

5. The solid-state imaging device according to claim 1, wherein the unit pixel cell has:

a first wiring layer located above the gate electrode of the amplification transistor and a gate electrode of the reset transistor; and

a second wiring layer located above the first wiring layer, and

the connection wiring is provided in the first wiring layer.

6. The solid-state imaging device according to claim 1, wherein the vertical signal line is located below the pixel electrodes of the unit pixel cells corresponding to the vertical signal line.

7. A solid-state imaging device comprising

a plurality of unit pixel cells arranged in a two-dimensional array, and

each of the pixel units cell including:

a photoelectric conversion film which is formed above a semiconductor substrate and photoelectrically converts an incident light;

a pixel electrode which is formed above the semiconductor substrate and is in contact with the photoelectric conversion film;

an amplification transistor which is formed on the semiconductor substrate, has a gate electrode connected to the pixel electrode, and outputs a signal voltage according to a potential of the pixel electrode; and

a reset transistor which is formed on the semiconductor substrate, and resets a potential of the gate electrode of the amplification transistor,

the solid-state imaging device further comprising;

a vertical signal line which is provided correspondingly to a column of the unit pixel cells and transmits a signal voltage of the unit pixel cells of the corresponding column; and

a row selection unit configured to select a row of the unit pixel cell having a signal voltage to be outputted to the vertical signal line,

wherein the vertical signal line is located below the pixel electrodes of the unit pixel cell adjacent to the unit pixel cells corresponding to the vertical signal line, and

includes wiring in a wiring layer other than a wiring layer in an uppermost region of a multi-layered wiring layer provided between (i) the amplification transistor and the reset transistor, and (ii) the pixel electrode.

8. The solid-state imaging device according to claim 7, wherein the vertical signal line includes wiring in a lowermost region of the multi-layered wiring layer provided between (i) the amplification transistor and the reset transistor, and (ii) the pixel electrode.

9. A solid-state imaging device comprising

a plurality of unit pixel cells arranged in a two-dimensional array, and

each of the pixel units cell including:

a photoelectric conversion film which is formed above a semiconductor substrate and photoelectrically converts an incident light;

a pixel electrode which is formed above the semiconductor substrate and is in contact with the photoelectric conversion film;

an amplification transistor which is formed on the semiconductor substrate, has a gate electrode connected to the pixel electrode, and outputs a signal voltage according to a potential of the pixel electrode; and

a reset transistor which is formed on the semiconductor substrate, and resets a potential of the gate electrode of the amplification transistor,

the solid-state imaging device further comprising;

a vertical signal line which is provided correspondingly to a column of the unit pixel cells and transmits a signal voltage of the unit pixel cells of the corresponding column; and

a row selection unit configured to select a row of the unit pixel cell having a signal voltage to be outputted to the vertical signal line,

wherein the vertical signal line is located below the pixel electrode of the unit pixel cell adjacent to the unit pixel cell corresponding to the vertical signal line, and

a shielding electrode which reduces capacitive coupling between the pixel electrode and the vertical signal line located below the pixel electrode is provided therebetween.

10. The solid-state imaging device according to claim 9, wherein the shielding electrode is wiring in the amplification transistor or the reset transistor.

11. A solid-state imaging device comprising

a plurality of unit pixel cells arranged in a two-dimensional array, and

each of the pixel units cell including:

a photoelectric conversion film which is formed above a semiconductor substrate and photoelectrically converts an incident light;

a pixel electrode which is formed above the semiconductor substrate and is in contact with the photoelectric conversion film;

an amplification transistor which is formed on the semiconductor substrate, has a gate electrode connected to the pixel electrode, and outputs a signal voltage according to a potential of the pixel electrode;

a reset transistor which is formed on the semiconductor substrate, and resets a potential of the gate electrode of the amplification transistor; and

wiring which electrically connects the amplification transistor, the reset transistor, and the selection transistor,

the solid-state imaging device further comprising;

a vertical signal line which is provided correspondingly to a column of the unit pixel cells and transmits a signal voltage of the unit pixel cells of the corresponding column; and

a row selection unit configured to select a row of the unit pixel cell having a signal voltage to be outputted to the vertical signal line,

wherein a thickness of the pixel electrode is less than a thickness of the wiring.

12. The solid-state imaging device according to claim 11, wherein an insulating layer is disposed between the pixel electrode and the wiring, so that the pixel electrode satisfies the following relationship:

s<

p×

W/T

where W is a width of wiring, T is a film pressure of the insulating layer, s is the thickness of the pixel electrode, and p is a distance between the pixel electrodes of the unit pixel cells adjacent to each other.

13. A solid-state imaging device comprising

a plurality of unit pixel cells arranged in a two-dimensional array,

each of the pixel units cell including:

a photoelectric conversion film which is formed above a semiconductor substrate and photoelectrically converts an incident light;

a pixel electrode which is formed above the semiconductor substrate and is in contact with the photoelectric conversion film;

an amplification transistor which is formed on the semiconductor substrate, has a gate electrode connected to the pixel electrode, and outputs a signal voltage according to a potential of the pixel electrode; and

a reset transistor which is formed on the semiconductor substrate, and resets a potential of the gate electrode of the amplification transistor through connection wiring connecting the amplification transistor and the reset transistor, at least a part of the connection wiring being located below a pixel electrode of an adjacent unit pixel cell,

the solid-state imaging device further comprising;

a vertical signal line which is provided correspondingly to a column of the unit pixel cells and transmits a signal voltage of the unit pixel cells of the corresponding column; and

a row selection unit configured to select a row of the unit pixel cell having a signal voltage to be outputted to the vertical signal line,

wherein

the connection wiring includes wiring in a wiring layer other than a wiring layer in an uppermost region of a multi-layered wiring layer provided between (i) the amplification transistor and the reset transistors, and (ii) the pixel electrode.

14. The solid-state imaging device according to claim 13, wherein the connection wiring includes wiring in a lowermost region of the multi-layered wiring layer provided between (i) the amplification transistor and the reset transistor, and (ii) the pixel electrode.

15. The solid-state imaging device according to claim 13, wherein a shielding electrode which reduces capacitive coupling between the pixel electrode and the connection wiring located below the pixel electrode is provided therebetween.

16. The solid-state imaging device according to claim 15, wherein the shielding electrode is wiring in the amplification transistor, the reset transistor, or the selection transistor.