Semiconductor device and insulated gate bipolar transistor with barrier regions

• US 9,105,679 B2
• Filed: 11/27/2013
• Issued: 08/11/2015
• Est. Priority Date: 11/27/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Laven, Johannes Georg, Baburske, Roman, Jaeger, Christian
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US14/091,955
• Publication Number:
  US 20150144988A1
• Time in Patent Office: 622 Days
• Field of Search: 257/367, 257/566, 257/592, 257/593
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes

Abstract

In a semiconductor device a barrier region is sandwiched between a drift region and a charge carrier transfer region. The barrier and charge carrier transfer regions form a pn junction. The barrier and drift regions form a homojunction. A mean impurity concentration in the barrier region is at least ten times as high as an impurity concentration in the drift region. A control structure is arranged to form an inversion layer in the drift and barrier regions in an inversion state. No inversion layer is formed in the drift and barrier regions in a non-inversion state.

Claims

1. A semiconductor device, comprising:

a barrier region sandwiched between a drift region and a charge carrier transfer region, the barrier and charge carrier transfer regions forming a pn junction and the barrier and drift regions forming a homojunction, wherein an impurity concentration in the barrier region is at least ten times as high as an impurity concentration in the drift region; and

a control structure configured to form an inversion layer in the drift and barrier regions in an inversion state and to form no inversion layer in the drift and barrier regions in a non-inversion state.

2. The semiconductor device of claim 1, wherein

the semiconductor device is configured not to form, through the charge carrier transfer region, a path for minority charge carriers in an inversion layer along the control structure between the drift region and a load electrode.

3. The semiconductor device of claim 1, wherein

the control structure extends from a first surface of a semiconductor body comprising the charge carrier transfer region into the semiconductor body down to at least the drift region, and

the charge carrier transfer region directly adjoins the first surface at the control structure.

4. The semiconductor device of claim 1, wherein

the control structure extends from a first surface of a semiconductor body comprising the charge carrier transfer region into the semiconductor body down to at least the drift region, and

the control structure comprises a control electrode, a control dielectric sandwiched between the barrier and drift regions on a first side and the control electrode at a second side opposite to the first side, and a top dielectric between the first surface and the control electrode overlaps the charge carrier transfer region in a vertical direction perpendicular to the first surface.

5. The semiconductor device of claim 1, wherein

the semiconductor device is a semiconductor diode comprising a cathode layer of a conductivity type of the drift and barrier regions between the drift region and a second surface of the semiconductor body opposite to the first surface.

6. The semiconductor device of claim 1, wherein

the semiconductor device is an insulated gate bipolar transistor comprising a field effect transistor cell.

7. The semiconductor device of claim 1, wherein

the semiconductor device is a reverse conducting insulated gate bipolar transistor comprising a collector layer comprising first zones of a first conductivity type and second zones of a second conductivity type complementary to the first conductivity type between the drift region and a second surface of the semiconductor body opposite to the first surface.

8. The semiconductor device of claim 1, wherein

the semiconductor device is a non-reverse conducting insulated gate bipolar transistor comprising a collector layer between the drift region and a second surface of the semiconductor body opposite to the first surface, wherein the collector layer has a second conductivity type complementary to a first conductivity type of the drift region.

9. The semiconductor device of claim 6, wherein

the transistor cell comprises a body region forming pn junctions with a source region and the drift region, and a gate structure configured to form an inversion layer in the body region during an on state and to form no inversion layer in the body region outside the on state of the transistor cell.

10. The semiconductor device of claim 9, wherein

the control structure comprises a control electrode and a control dielectric between the barrier and drift regions on a first side and the control electrode at a second side opposite to the first side,

the gate structure comprises a gate electrode and a gate dielectric between the body region on a first side and the gate electrode at a second side opposite to the first side, and

the gate and control structures are electrically connected to each other.

11. The semiconductor device of claim 9, wherein

a voltage higher than a first threshold voltage at the gate and control structures induces the on state,

a voltage lower than a second threshold voltage, which is lower than the first threshold voltage, induces the inversion state, and

a voltage between the first and second threshold induces neither the on state nor the inversion state.

12. The semiconductor device of claim 9, wherein

a voltage higher than a first threshold voltage at the gate and control structures induces the on state,

a voltage lower than a second threshold voltage, which is higher than the first threshold voltage, induces the inversion state, and

a voltage higher than the second threshold voltage induces the non-inversion state.

13. The semiconductor device of claim 10, wherein

the gate and control dielectrics are provided from different materials and/or the gate and control electrodes are formed from different materials such that a first threshold voltage of the transistor cell is equal to or lower than a second threshold voltage of the auxiliary cell.

14. The semiconductor device of claim 10, wherein

the control dielectric contains fixed negative charges and/or a work function of a material of the control electrode with respect to the semiconductor body is higher than a work function of a material of the gate electrode.

15. The semiconductor device of claim 10, further comprising:

a voltage shifter configured to apply a voltage to the control electrodes that deviates from a voltage applied to the gate electrodes by a predefined voltage offset, wherein the voltage offset is greater than a difference between the first and second threshold voltages.

16. The semiconductor device of claim 1, further comprising:

a plurality of auxiliary cells, each auxiliary cell comprising one of the control structures, wherein

a population density of the auxiliary cells in a central region of an active area is higher than in an outer region of the active area oriented to an edge area devoid of auxiliary cells.

17. The semiconductor device of claim 1, wherein

the barrier region contains impurities of a deep level donor or deep double donor.

18. An insulated gate bipolar transistor, comprising:

a transistor cell; and

an auxiliary cell comprising a barrier region sandwiched between a drift region and a charge carrier transfer region, the barrier and charge carrier transfer regions forming a pn junction and the barrier and drift regions forming a homojunction, wherein an impurity concentration in the barrier region is at least ten times as high as an impurity concentration in the drift region.

19. The insulated gate bipolar transistor of claim 18, wherein

a control structure of the auxiliary cell comprises a control electrode and a control dielectric between the barrier and drift regions on a first side and the control electrode at a second side opposite to the first side, and

the control electrode is electrically connected to a fixed potential with respect to a load electrode.

20. A semiconductor diode, comprising:

a control structure extending from a first surface into a semiconductor body, the control structure comprising a control electrode and a control dielectric between the semiconductor body on a first side and the control electrode at a second side opposite to the first side; and

a barrier region sandwiched between a drift region and a charge carrier transfer region in the semiconductor body, the barrier and charge carrier transfer regions forming a pn junction and the barrier and drift regions forming a homojunction, wherein an impurity concentration in the barrier region is at least ten times as high as an impurity concentration in the drift region.