Semiconductor structure with reduced junction leakage and method of fabrication thereof

• US 9,105,711 B2
• Filed: 12/19/2013
• Issued: 08/11/2015
• Est. Priority Date: 08/31/2012
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Wang, Lingquan, Bakhishev, Teymur, Zhao, Dalong, Ranade, Pushkar, Pradhan, Sameer, Hoffmann, Thomas, Shifren, Lucian, Scudder, Lance
• Primary Examiner(s): Reames, Matthew
• Assistant Examiner(s): Schoenholtz, Joseph
• Application Number:
  US14/133,743
• Publication Number:
  US 20140103406A1
• Time in Patent Office: 600 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion implantation.

Claims

1. A method for forming a facet free field effect transistor structure using selective epitaxial deposition, comprising:

providing a substrate;

epitaxially growing, over distinct areas of the substrate, a plurality of first epitaxial screen layers for a plurality of field effect transistors, the respective first epitaxial screen layers having defined dopant concentrations and grown to preselected thicknesses;

epitaxially growing, over distinct areas of the first epitaxial screen layers, a plurality of second epitaxial channel layers, the respective second epitaxial channel layers being undoped and grown to preselected thicknesses;

wherein at least some of the epitaxially grown layers form facets that are eliminated during processing.

2. The method of claim 1, wherein epitaxially growing the first epitaxial screen layers for the field effect transistors further introduces dopant species into the selective epitaxial deposition process.

3. The method of claim 2, further comprising:

forming a blanket epitaxial layer on the substrate.

4. The method of claim 1, further comprising:

etching through a portion of the second epitaxial channel layers and the first epitaxial screen layers through to the substrate to eliminate the facets formed by the epitaxial growth of the second epitaxial channel layers.

5. The method of claim 1, further comprising:

turning on a dopant source during epitaxial growth of the first epitaxial screen layer of at least one of a first field effect transistor and a second field effect transistor;

turning off a dopant source during epitaxial growth of the second epitaxial channel layer of the at least one of the first and second field effect transistors.

6. The method of claim 5, wherein epitaxial growth is continuously performed for the first epitaxial screen layer and the second epitaxial channel layer of the first and second field effect transistors.

7. The method of claim 5, wherein a thickness of the first epitaxial screen layer and the second epitaxial channel layer of the first and second field effect transistors is determined by when the dopant source is turned off.

8. The method of claim 7, wherein the thickness for the second epitaxial screen layer of the first field effect transistor is different than the thickness for the second epitaxial screen layer of the second field effect transistor.

9. The method of claim 1, further comprising:

forming by epitaxial growth a threshold voltage control layer between the first epitaxial screen layer and the second epitaxial channel layer for at least one of a first field effect transistor and a second field effect transistor, the threshold voltage control layer having a dopant concentration less than a dopant concentration of the first epitaxial screen layer.

10. The method of claim 9, further comprising:

using a first doping condition during epitaxial growth of the first epitaxial screen layer for the at least one of the first and second field effect transistors;

using a second doping condition during epitaxial growth of the threshold voltage control layer for the at least one of the first and second field effect transistors.

11. The method of claim 9, wherein epitaxial growth is continuously performed for the first epitaxial screen layer, the threshold voltage control layer, and the second epitaxial channel layer for the at least one of the first and second field effect transistors.

12. The method of claim 1, further comprising:

forming a threshold voltage control layer for at least one of a first field effect transistor and a second field effect transistor, the threshold voltage control layer having a dopant concentration that is less than a dopant concentration of the first epitaxial screen layer for the at least one of the first and second field effect transistors, the threshold voltage control layer being formed by ion implantation.

13. An intermediate die structure for a field effect transistor, comprising:

a substrate;

a plurality of areas temporarily protecting portions of the substrate from having deposited thereon a single crystal silicon material;

a plurality of first epitaxial screen layers deposited on the substrate and defined between the plurality of areas, the respective first epitaxial screen layers having defined dopant concentrations and preselected thickness;

a plurality of second epitaxial channel layers, the respective second epitaxial channel layers having no facets, configured to be undoped, and to have preselected thicknesses, the plurality of second epitaxial channel layers being disposed on the plurality of first epitaxial screen layers;

a blanket epitaxial layer positioned above the substrate.

14. The structure of claim 13, wherein the first epitaxial screen layers have no implanted dopants.

15. The structure of claim 13, wherein the respective second epitaxial channel layers have the same thickness.

16. A facet free channel structure for a field effect transistor, comprising:

a substrate;

a plurality of first screen layers deposited on the substrate, the respective first screen layers having defined dopant concentrations and preselected thicknesses; and

a plurality of second epitaxial channel layers, the respective second epitaxial channel layers having no facets, being substantially undoped, and having preselected thicknesses, the plurality of second epitaxial channel layers being selectively deposited on the plurality of first screen layers;

wherein the first screen layers are part of a blanket epitaxial layer positioned above the substrate.

17. The structure of claim 16, wherein the first screen layers have no implanted dopants.

18. The structure of claim 16, wherein the respective second epitaxial channel layers have the same thickness.