Semiconductor device and method for manufacturing the same

• US 9,105,715 B2
• Filed: 04/30/2009
• Issued: 08/11/2015
• Est. Priority Date: 04/30/2009
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Miura, Naruhisa, Nakata, Shuhei, Ohtsuka, Kenichi, Watanabe, Shoyu, Yutani, Naoki
• Primary Examiner(s): YUSHINA, GALINA G
• Application Number:
  US13/146,654
• Publication Number:
  US 20110284874A1
• Time in Patent Office: 2,294 Days
• Field of Search: 257/328, 257/329, 257/331, 257/339, 257/341, 257/351, 257/355, 257/356, 257/367, 257/368, 257/401, 257/409, 257/502, 257/E29.008, 257/E29.257, 257/E21.418, 438/142, 438/156, 438/173, 438/585, 438/630, 438/657
• US Class Current: 1/1
• CPC Class Codes: H01L 23/53209 based on metals, e.g. alloys, metal silicides H01L23/53285 takes precedence
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is on the field oxide film, going around a periphery of the cell region, and electrically connected to the second gate electrode. The gate wiring is a silicide of a constituting substance of the second gate electrode.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a first major surface and a second major surface facing each other;

a drift layer of a first conductivity type on the first major surface;

a cell region in one upper portion of the drift layer and in the center of the semiconductor device;

a well of a second conductivity type in another upper portion of the drift layer disposed in a peripheral region of the semiconductor device;

a first electrode above the first major surface of the semiconductor substrate, the first electrode is electrically connected to the well;

a second electrode under the second major surface of the semiconductor substrate;

an insulating film on the well; and

a gate electrode and a gate wiring provided on the insulating film,

wherein the gate wiring is a silicide created from a portion of a poly-silicon layer used for the gate electrode, and

the gate wiring is electrically connected to the gate electrode in the horizontal direction and does not overlap with the gate electrode.

2. The semiconductor device according to claim 1, wherein the first electrode is connected to the well in an interior side of the gate electrode and the insulating film.

3. The semiconductor device according to claim 1, wherein the semiconductor substrate is SiC.

4. The semiconductor device according to claim 1, wherein the gate electrode is formed from the poly-silicon layer.

5. The semiconductor device according to claim 1, wherein the gate electrode includes laminated films including the poly-silicon layer, a metal layer, and a metal nitride layer,

the metal layer including a metal which is at least one of Ti, Mo, W, Nb, and Ta, and

the metal nitride layer including a nitride of the metal.

6. The semiconductor device according to claim 1, further comprising:

a diffusion region, which is a source region, wherein

the first electrode is a source electrode, and the second electrode is a drain electrode.

7. The semiconductor device according to claim 1, further comprising a second well of the second conductivity type in an upper portion of the cell region in the drift layer;

a diffusion region of the first conductivity type in the second well, and a collector layer of the second conductivity type between the second major surface of the semiconductor substrate and the second electrode,

wherein the diffusion region is an emitter region, the first electrode is an emitter electrode, and the second electrode is a collector electrode.

8. The semiconductor device according to claim 1, further comprising:

a second well of the second conductivity type in an upper portion of the cell region in the drift layer, and a diffusion region of the first conductivity type in the second well, wherein the diffusion region is a source region, the first electrode is a source electrode, and the second electrode is a drain electrode.

9. A method for manufacturing a semiconductor device comprising:

preparing a semiconductor substrate of a first conductivity type having a first major surface and a second major surface facing to each other;

forming a first well of a second conductivity type in an upper surface of the first major surface in a cell region of the first major surface and a second well of a second conductivity type in the upper surface of the first major surface on a peripheral portion of the cell region;

forming a diffusion region of a first conductivity type in the upper surface of the first major surface in the first well;

forming a first gate insulating film on the first well and a second gate insulating film on the second well;

forming a field oxide film on the second well on the peripheral side of the second gate insulating film and being thicker than the second gate insulating film;

forming a first gate electrode on the first gate insulating film;

forming a second gate electrode sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode;

forming an interlayer insulating film on the first major surface so as to cover the first gate electrode and the second gate electrode;

etching the interlayer insulating film to form a first contact hole on the first well and the diffusion region and a second contact hole on the second well;

etching the interlayer insulating film to expose a part of the second gate electrode;

forming a gate wiring going around a periphery of the cell region on the field oxide film by a silicidation of the exposed part of the second gate electrode;

forming a first electrode electrically connected to the first well and the diffusion region via the first contact hole and electrically connected to the second well via the second contact hole;

forming a second electrode on the second major surface of the semiconductor substrate; and

forming a gate pad electrically connected to the gate wiring.

10. The method for manufacturing a semiconductor device according to claim 9, further comprising:

etching the interlayer insulating film to form the first contact hole and the second contact hole without exposing the second gate electrode;

siliciding the surface of the semiconductor substrate exposed in the first contact hole and the second contact hole;

etching the interlayer insulating film to expose a part of the second gate electrode after the silicidation of the surface of the semiconductor substrate; and

forming the gate wiring by the silicidation of the exposed part of the second gate electrode.