Semiconductor device

• US 9,105,716 B2
• Filed: 11/11/2010
• Issued: 08/11/2015
• Est. Priority Date: 12/10/2007
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Akiyama, Miwako, Kawaguchi, Yusuke, Yamaguchi, Yoshihiro
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): Kalam, Abul
• Application Number:
  US12/944,632
• Publication Number:
  US 20110059586A1
• Time in Patent Office: 1,734 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the second conductivity type provided in an interior portion of the second semiconductor layer corresponding to a part under the contact groove. An uppermost portion of the fifth semiconductor layer contacts the third semiconductor layer, a lowermost portion of the fifth semiconductor layer has a higher impurity concentration than that of the other portion in the fifth semiconductor layer and is located in the second semiconductor layer and not contacting the first semiconductor layer, and the fifth semiconductor layer is narrower from the uppermost portion to the lower most portion.

Claims

1. A method for producing a semiconductor device, comprising:

forming a first trench gate structure and a second trench gate structure in a plurality of semiconductor layers including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type on the first semiconductor layer, a third semiconductor layer of a second conductivity type on the second semiconductor layer, and a fourth semiconductor layer of the first conductivity type on the third semiconductor layer, the second semiconductor layer having a first conductivity type impurity concentration that is lower than a first conductivity type impurity concentration of the first semiconductor layer, the first and second trench gate structures extending along a first direction from a first surface of the fourth semiconductor through the third semiconductor layer and reaching the second semiconductor layer and being spaced from each other along a second direction that is parallel to the first surface and crossing the first direction;

forming a contact groove passing through the fourth semiconductor layer between the first and second trench gate structures and reaching the third semiconductor layer, the contact groove having a width along the second direction, that narrows with increasing distance along the first direction into the fourth semiconductor layer; and

forming a fifth semiconductor layer in the second semiconductor layer by introducing an impurity of the second conductivity type through the contact groove and the fourth semiconductor layer to a plurality of introduction positions spaced along the first direction within the second semiconductor layer, the introducing occurring in a sequence such that each introduction position in the sequence is at a distance from the first semiconductor layer that is greater than any preceding introduction position within the sequence, the fourth semiconductor layer, in which the contact groove is formed, serving as a mask during the introducing of the impurity of the second conductivity type to the plurality of introduction positions,

the fifth semiconductor layer having a first portion and a second portion that is closer along the first direction to the first semiconductor layer than is the first portion, the first portion being wider along the second direction than the second portion, and

a dose amount at a first introduction position in the sequence of the introducing of the impurity of the second conductivity type being higher than a dose amount at any subsequent introduction position in the sequence.

2. The method for producing a semiconductor device according to claim 1, wherein a width along the second direction of the fifth semiconductor layer decreases in a stepwise manner along the first direction.

3. The method for producing a semiconductor device according to claim 1, wherein the width of the contact groove is narrowed continuously.

4. The method for producing a semiconductor device according to claim 1, wherein the width of the contact groove is narrowed in a stepwise manner.

5. The method for producing a semiconductor device according to claim 1, wherein the introducing of the impurity of the second conductivity type at the plurality of introduction positions is performed by ion implantation.

6. The method for producing a semiconductor device according to claim 5, wherein the implanted impurity more largely diffuses to the horizontal direction as the position implanted is shallower.

7. The method for producing a semiconductor device according to claim 5, further comprising diffusing the implanted impurity by heat treatment after the sequence of the introducing of the impurity of the second conductivity type at the plurality of introduction positions is performed by ion implantation, but not during the sequence.