Semiconductor device having metal gate and manufacturing method thereof

• US 9,105,720 B2
• Filed: 09/11/2013
• Issued: 08/11/2015
• Est. Priority Date: 09/11/2013
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lin, Chun-Hsien, Liu, An-Chi
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): Harrison, Monica D
• Application Number:
  US14/023,481
• Publication Number:
  US 20150069533A1
• Time in Patent Office: 699 Days
• Field of Search: 257 40- 42, 257/59, 257/66, 257/72, 257/410, 438/591
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method for manufacturing a semiconductor device having metal gate includes following steps. A substrate having at least a first semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench formed therein. Next, an n-typed work function metal layer is formed in the first gate trench. After forming the n-typed work function metal layer, a nitridation process is performed to form a first protecting layer on the n-typed work function metal layer. After forming the first protecting layer, an oxidation process is performed to the first protecting layer to form a second protecting layer on the n-typed work function metal layer. Then, a gap filling metal layer is formed to fill up the first gate trench.

Claims

1. A method for manufacturing a semiconductor device having metal gate, comprising:

providing a substrate having at least a first semiconductor device formed thereon, and the first semiconductor device comprising a first gate trench formed therein;

sequentially forming a bottom barrier layer, an etch stop layer, and a p-typed work function metal layer on the substrate;

forming an n-typed work function metal layer in the first gate trench after forming the p-typed work function metal layer;

performing a nitridation process to form a first protecting layer on the n-typed work function metal layer;

performing an oxidation process to the first protecting layer to form a second protecting layer on the n-typed work function metal layer after the nitridation; and

forming a gap-filling metal layer to fill up the first gate trench.

2. The method for manufacturing a semiconductor device having metal gate according to claim 1, further comprising forming a high-k gate dielectric layer in the first gate trench before forming the n-type work function metal layer.

3. The method for manufacturing a semiconductor device having metal gate according to claim 1, further comprising a high-k gate dielectric layer, and the high-k gate dielectric layer is exposed in the first gate trench.

4. The method for manufacturing a semiconductor device having metal gate according to claim 1, wherein the nitridation process comprises N₂ or NH₃.

5. The method for manufacturing a semiconductor device having metal gate according to claim 1, wherein the oxidation process comprises N₂O or O₂.

6. The method for manufacturing a semiconductor device having metal gate according to claim 1, further comprising a second semiconductor device formed on the substrate, and the second semiconductor device comprises a second gate trench formed therein.

7. The method for manufacturing a semiconductor device having metal gate according to claim 1, further comprising removing the p-typed work function metal layer from the first gate trench before forming the n-typed work function metal layer.

8. A semiconductor device having metal gate comprising:

a substrate;

a high-k gate dielectric layer formed on the substrate;

an n-typed work function metal layer formed on the high-k gate dielectric layer;

a first protecting layer formed on the n-typed work function metal layer, the first protecting layer comprising a nitrified material of the n-typed work function metal layer;

a second protecting layer formed on the first protecting layer, the second protecting layer comprising an oxidized material of the first protecting layer, wherein the second protecting layer is a TiAlNO layer; and

a gap-filling metal layer directly formed on the second protecting layer.

9. The semiconductor device having metal gate according to claim 8, wherein the high-k gate dielectric layer comprises a flat shape or a U shape.

10. The semiconductor device having metal gate according to claim 8, wherein the n-typed work function metal layer comprises TiAl layer.

11. The semiconductor device having metal gate according to claim 10, wherein the first protecting layer is a TiAlN layer.

12. The semiconductor device having metal gate according to claim 8, wherein an overall thickness of the first protecting layer and the second protecting layer is smaller than a half of a thickness of the n-typed work function metal layer.

13. The semiconductor device having metal gate according to claim 8, further comprising at least a bottom barrier layer and an etch stop layer formed between the high-k gate dielectric layer and the n-typed work function metal layer.