Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure

• US 9,105,751 B2
• Filed: 11/11/2011
• Issued: 08/11/2015
• Est. Priority Date: 11/11/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Harame, David L., Stamper, Anthony K.
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): Parker, John M
• Application Number:
  US13/294,603
• Publication Number:
  US 20130122627A1
• Time in Patent Office: 1,369 Days
• Field of Search: 438/50, 438/52, 438/53
• US Class Current: 1/1
• CPC Class Codes: B81B 2201/0285 Vibration sensors
• CPC Class Codes: B81B 3/0027 Structures for transforming mechanical energy, e.g. potential energy of a spring into translation, sound into translation
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H03H 2001/0064 comprising semiconductor material
• CPC Class Codes: H03H 2003/027 the resonators or networks being of the microelectro-mechanical [MEMS] type
• CPC Class Codes: H03H 2009/155 using MEMS techniques
• CPC Class Codes: H03H 2009/241 Bulk-mode MEMS resonators
• CPC Class Codes: H03H 3/02 for the manufacture of piezoelectric or electrostrictive resonators or networks H03H3/08 takes precedence
• CPC Class Codes: H03H 9/1007 for bulk acoustic wave [BAW] devices
• CPC Class Codes: H03H 9/173 Air-gaps
• CPC Class Codes: H10N 30/306 Cantilevers

Abstract

Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, methods of manufacture and design structure are provided. The method includes forming a single crystalline beam from a silicon layer on an insulator. The method further includes providing a coating of insulator material over the single crystalline beam. The method further includes forming a via through the insulator material exposing a wafer underlying the insulator. The insulator material remains over the single crystalline beam. The method further includes providing a sacrificial material in the via and over the insulator material. The method further includes providing a lid on the sacrificial material. The method further includes venting, through the lid, the sacrificial material and a portion of the wafer under the single crystalline beam to form an upper cavity above the single crystalline beam and a lower cavity in the wafer, below the single crystalline beam.

Claims

1. A method comprising:

forming a single crystalline beam from a silicon layer on an insulator;

providing a coating of insulator material over the single crystalline beam;

forming a via through the insulator material exposing a wafer underlying the insulator, wherein the insulator material remains over the single crystalline beam;

providing a sacrificial material in the via and over the insulator material;

providing a lid on the sacrificial material; and

venting, through the lid, the sacrificial material and a portion of the wafer under the single crystalline beam to form an upper cavity above the single crystalline beam and a lower cavity in the wafer, below the single crystalline beam.

2. The method of claim 1, further comprising forming one or more devices in the silicon layer, separated from the single crystalline beam by one or more shallow trench isolation structures.

3. The method of claim 2, further comprising forming a Bulk Acoustic Wave (BAW) filter or Bulk Acoustic Resonator (BAR) in electrical connection with at least one of the one or more devices.

4. The method of claim 1, wherein forming of the single crystalline beam further comprises forming layers of metal and piezoelectric material over the silicon layer.

5. The method of claim 4, wherein the forming of the metal layers and piezoelectric material comprises:

depositing a first metal layer over an insulator layer on the single crystalline beam;

depositing the piezoelectric material on the first metal layer;

depositing a second metal layer on the piezoelectric material; and

patterning the first metal layer, the piezoelectric material, the second metal layer and the insulator layer.

6. The method of claim 5, further comprising forming a trench through the first metal layer, the piezoelectric material, the second metal layer and the insulator layer, and wherein the insulator material is formed over exposed portions of at least the first metal layer, the piezoelectric material and the second metal layer, and further fills the trench.

7. The method of claim 1, wherein the insulator material is oxide deposited using high density plasma or plasma enhanced high density plasma processes or low pressure chemical vapor deposition (CVD) processes.

8. The method of claim 1, wherein the insulator material is patterned using a reverse mask and RIE process prior to the forming of the via.

9. The method of claim 8, wherein the insulator material undergoes a chemical mechanical polish (CMP) with an optional oxide deposition process prior to forming the via.

10. The method of claim 9, wherein the forming the via comprises etching of the insulator and portions of the insulator material such that sidewalls of the via and exposed portions of the single crystalline beam remain coated in the insulator material.

11. The method of claim 1, wherein the sacrificial material is silicon deposited in the via and on the insulator material.

12. The method of claim 1, wherein the venting comprises forming a vent hole in the lid, etching of the sacrificial material using a XeF₂ etchant through the vent hole, which will strip all of the exposed sacrificial material, and plugging the vent hole after the formation of the upper cavity and the lower cavity.

13. The method of claim 12, wherein the insulator material protects the single crystalline beam and any constituent layers during the venting.

14. The method of claim 1, wherein the upper cavity and the lower cavity are formed in a single venting step.

15. A method, comprising:

forming a single crystalline beam from a single crystalline silicon layer of an SOI substrate; and

protecting the single crystalline beam with an insulator material during cavity formation, wherein;

the cavity formation comprises forming an upper cavity and a lower cavity above and below the single crystalline beam, respectively;

the upper cavity is formed above a BOX layer of the SOI substrate, by etching of a sacrificial layer formed over the insulator material that coats and protects exposed portions of the single crystalline beam;

the lower cavity is formed below the BOX layer by etching a portion of bulk substrate through a connecting via formed between the upper cavity and the lower cavity, the connecting via is lined with the insulator material that coats and protects the exposed portions of the single crystalline beam; and

the etching of the sacrificial layer and the etching of the portion of the bulk substrate are included in a single venting process.

16. The method of claim 15, further comprising:

forming one or more devices in the single crystalline silicon layer of the SOI substrate, separated from the single crystalline beam by one or more shallow trench isolation structures; and

forming a Bulk Acoustic Wave (BAW) filter or Bulk Acoustic Resonator (BAR) in electrical connection with at least one of the one or more devices.

17. The method of claim 15, wherein the forming of the single crystalline beam further comprises forming layers of metal and piezoelectric material over the single crystalline silicon layer of the SOI substrate, wherein the forming of the metal layers and piezoelectric material comprises:

depositing a first metal layer over an insulator layer formed on the single crystalline beam;

depositing the piezoelectric material on the first metal layer;

depositing a second metal layer on the piezoelectric material; and

patterning of the first metal layer, the piezoelectric material and the second metal layer.

18. The method of claim 17, further comprising forming a trench through the first metal layer, the piezoelectric material, the second metal layer and the insulator layer, and the insulator material is formed within the trench and over exposed portions of at least the first metal layer, the piezoelectric material and the second metal layer.

19. The method of claim 15, wherein the connecting via is formed through the insulator material, to expose the bulk substrate, the forming results in sidewalls of the via being coated with the insulator material.

20. The method of claim 15, wherein the insulator material is oxide deposited using high density plasma or plasma enhanced high density plasma processes or low pressure chemical vapor deposition (CVD) processes.