Method for bonding semiconductor substrates

• US 9,105,827 B2
• Filed: 07/02/2014
• Issued: 08/11/2015
• Est. Priority Date: 11/29/2011
• Status: Active Grant

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: Pham, Nga Phuong, Rosmeulen, Maarten, Vandevelde, Bart
• Primary Examiner(s): Roman, Angel
• Application Number:
  US14/322,787
• Publication Number:
  US 20140312359A1
• Time in Patent Office: 405 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 33/005 Processes
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A method is provided for bonding a first substrate carrying a semiconductor device layer on its front surface to a second substrate. The method comprises producing the semiconductor device layer on the front surface of the first substrate, depositing a first metal bonding layer or a stack of metal layers on the first substrate, on top of the semiconductor device layer, depositing a second metal bonding layer or a stack of metal layers on the front surface of the second substrate, depositing a metal stress-compensation layer on the back side of the second substrate, thereafter establishing a metal bond between the first and second substrate, by bringing the first and second metal bonding layers or stacks of layers into mutual contact under conditions of mechanical pressure and temperature suitable for obtaining the metal bond, and removing the first substrate.

Claims

1. A layer stack for use in the manufacture of a semiconductor device, comprising:

a first substrate;

a semiconductor device layer on a front surface of the first substrate;

a first bonding stack of one or more metal la ers on toy of the semiconductor device layer;

a second bonding stack of one or more metal layers on a front surface of a second substrate;

a metal stress compensation layer on a back surface of the second substrate; and

a metal bond between the first substrate and the second substrate,

wherein at least one of the second bonding stack of one or more metal la ers and the first bondin stack of one or more metal la ers com rises a Cu la er and a Sn la er wherein the Sn layer is on top of and in direct contact with the Cu layer.

4. The layer stack of claim 1, wherein the device is a GaNLED device.

13. The layer stack of claim 1, wherein the first substrate is a wafer.

2. A layer stack for use in the manufacture of a semiconductor device, comprising:

a first substrate;

a semiconductor device layer on a front surface of the first substrate;

a first bonding stack of one or more metal layers on top of the semiconductor device layer;

a second bondind stack of one or more metal layers on a front surface of a second substrate;

a metal stress compensation layer on a back surface of the second substrate;

a protection layer on the metal stress compensation layer; and

a metal bond between the first substrate and the second substrate.

11. The layer stack of claim 2, wherein the protection layer is a SiN layer.

14. The layer stack of claim 2, wherein the first substrate is a wafer.

17. The layer stack of claim 2, wherein the device is a GaNLED device.

3. A layer stack for use in the manufacture of a semiconductor device, comprising:

a first substrate;

a semiconductor device layer on a front surface of the first substrate;

a first bonding stack of one or more metal layers on top of the semiconductor device layer;

a second bonding stack of one or more metal layers on a front surface of a second substrate;

a metal stress compensation layer on a back surface of the second substrate;

a diffusion-inhibiting layer situated between the second substrate and the metal stress compensation layer; and

a metal bond between the first substrate and the second substrate.

12. The layer stack of claim 3, wherein the diffusion-inhibiting layer is a SiN layer.

15. The layer stack of claim 3, wherein the first substrate is a wafer.

18. The layer stack of claim 3, wherein the device is a GaNLED device.

5. A layer stack for use in the manufacture of a semiconductor device, comprising:

a first substrate;

a semiconductor device layer on a front surface of the first substrate;

a first bonding stack of one or more metal layers on top of the semiconductor device layer;

a second bonding stack of one or more metal layers on a front surface of a second substrate;

a metal stress compensation layer on a back surface of the second substrate; and

a metal bond between the first substrate and the second substrate.

6. The layer stack of claim 5, wherein the metal bond is formed by bringing the first bonding stack of one or more metal layers and the second bonding stack of one or more metal layers into mutual contact under conditions of mechanical pressure and temperature.

7. The layer stack of claim 5, wherein the metal stress compensation layer is a single layer of a same material as a topmost metal layer of the second bonding stack of one or more metal layers.

8. The layer stack of claim 5, wherein a thickness of the metal stress compensation layer is less than or equal to a thickness of a topmost metal layer of the second bonding stack of one or more metal layers.

9. The layer stack of claim 5, wherein a thickness of the metal stress compensation layer is equal to a sum of a thickness of a topmost metal layer of the second bonding stack of one or more metal layers and a thickness of a topmost metal layer of the first bonding stack of one or more metal layers.

10. The layer stack of claim 5, wherein a thickness of the metal stress compensation layer is equal to a sum of a thickness of the second bonding stack of one or more metal layers and a thickness of the first bonding stack of one or more metal layers.

16. The layer stack of claim 5, wherein the first substrate is a wafer.

19. The layer stack of claim 5, wherein the device is a GaNLED device.