Methods and systems for high bandwidth chip-to-chip communications interface

• US 9,106,220 B2
• Filed: 02/11/2014
• Issued: 08/11/2015
• Est. Priority Date: 05/20/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Fox, John, Holden, Brian, Hunt, Peter, Keay, John D., Shokrollahi, Amin, Stewart, Andrew Kevin John, Surace, Giuseppe, Ulrich, Roger, Simpson, Richard
• Primary Examiner(s): ODOM, CURTIS B
• Application Number:
  US14/178,051
• Publication Number:
  US 20140226734A1
• Time in Patent Office: 546 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04L 67/12 specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values.

Claims

1. A system for interconnection of integrated circuit devices, comprising:

an interconnection comprising one or more interconnection wire groups, each interconnection wire group configured to communicate signals representing a code word of a vector signaling code;

an encoder configured to convert a current input data word into a transmit code word of the vector signaling code by modifying a portion of elements of a previously transmitted code word based on a set of difference bits representing a change of value from a previous input data word and the current input data word; and

,

a transmit driver configured to emit signals on interconnection wires of an interconnection wire group of the one or more interconnection wire groups that correspond to elements of the transmit code word.

2. The system of claim 1, wherein the vector signaling code is a balanced code and comprises elements from a set of at least three distinct values.

3. The system of claim 2, wherein the transmit driver is configured such that interaction of the balanced code elements emitted on an interconnection wire group passively generates at least one of the signals of that interconnection wire group.

4. The system of claim 1, wherein the encoder is configured to modify the portion of elements of the previously transmitted code word based on modulus addition.

5. The system of claim 1, wherein the encoder is configured to select the portion of elements of the previously transmitted code word based on values of the set of difference bits.

6. The system of claim 1, wherein consecutive transmissions comprise exactly one wire transition within a given wire group.

7. The system of claim 1, wherein the encoder further comprises history storage elements configured to store the transmit code word to be used as a previously transmitted code word in a subsequent transmission interval.

8. The system of claim 7, wherein the history storage elements comprise a plurality of flip-flops.

9. The system of claim 1, further comprising:

a receiver configured to detect signals on an interconnection of wires, the signals being elements of the transmit code word of the vector signaling code; and

,

a decoder configured to interpret the transmit code word as representing differences to be applied to a previous received data word to obtain a received data word.

10. The system of claim 9, further comprising a memory configured to store the current input data word to be a previous input data word for a subsequent transmission interval, the memory configured with an initial value equal to a preselected code word.

11. A method comprising:

encoding a current input data word as at least one transmit code word of a vector signaling code, the transmit code word comprising symbols from an alphabet of three or more distinct values, by modifying a portion of elements of a previously transmitted code word based on a set of difference bits representing a change of value from a previous input data word and the current input data word; and

,

transmitting symbols of the at least one transmit code word on at least one set of wires.

12. The method of claim 11, wherein the vector signaling code is a balanced code.

13. The method of claim 12, wherein at least one of the symbols of the transmit code word is passively achieved during transmission.

14. The method of claim 11, further comprising:

receiving the at least one transmit code word by at least one receiving integrated circuit device; and

,

decoding the at least one transmit code word to a current input data word.

15. The method of claim 14, wherein decoding comprises interpreting the at least one transmit code word as a representation of modifications to be applied to a previous input data word to obtain the current input data word.

16. The method of claim 15, further comprising storing the current input data word in a memory to be used as a previous input data word for a subsequent transmission interval.

17. The method of claim 16, further comprising initializing the memory with an initial value equal to a preselected code word.

18. The method of claim 11, wherein modifying the portion of elements of the previously transmitted code word is based on modulus addition.

19. The method of claim 11, further comprising selecting the portion of elements of the previously transmitted code word based on values of the set of difference bits.

20. The method of claim 11, wherein exactly one symbol of the transmit code word changes in a single transmission.