Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals

• US 9,106,227 B2
• Filed: 02/11/2014
• Issued: 08/11/2015
• Est. Priority Date: 02/28/2008
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Ranta, Tero Tapio, Bawell, Shawn, Greene, Robert W., Brindle, Christopher N., Englekirk, Robert Mark
• Primary Examiner(s): Puentes, Daniel
• Application Number:
  US14/178,116
• Publication Number:
  US 20140312958A1
• Time in Patent Office: 546 Days
• Field of Search: 327/427
• US Class Current: 1/1
• CPC Class Codes: H01F 21/12 discontinuously variable, e.g. tapped
• CPC Class Codes: H01G 4/002 Details
• CPC Class Codes: H01G 7/00 Capacitors in which the capacitance is varied by non-mechanical means; Processes of their manufacture
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H03H 11/28 Impedance matching networks
• CPC Class Codes: H03H 7/0153 Electrical filters; Controlling thereof
• CPC Class Codes: H03H 7/38 Impedance-matching networks
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/20 of single resonant circuit by varying inductance only or capacitance only
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03M 1/1061 using digitally programmable trimming circuits
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Claims

1. A circuit coupled between a first terminal and a second terminal, comprising:

a plurality of stacked elements, the stacked elements proceeding from a first element of the stacked elements, closest the first terminal and farthest from the second terminal to an n-th element of the stacked elements farthest from the first terminal and closest to the second terminal,

a plurality of compensating capacitors associated with the stacked elements,

wherein;

nodes between the elements exhibit parasitic capacitances,

the first terminal is a terminal through which a voltage source is coupled to the circuit;

the stacked elements comprise a first set of elements close to the first terminal and far from the second terminal and a second set of elements far from the first terminal and close to the second terminal,

the compensating capacitors comprise a first set of compensating capacitors associated with the first set of elements and a second set of compensating capacitors associated with the second set of elements,

the first set of compensating capacitors comprises i capacitors (i=1, 2, . . . ), the first capacitor of the first set of capacitors being located in parallel with a first element of the first set of elements, the second capacitor of the first set of capacitors being located in parallel with a series of the first element and a second element of the first set of elements, the third capacitor of the first set of capacitors being located in parallel with a series of the first element, the second element and a third element of the first set of elements and so on,

the second set of compensating capacitors comprises i corresponding capacitors (i=1, 2, . . . ), the first capacitor of the second set of capacitors being located in parallel with a first element of the second set of elements, the second capacitor of the second set of capacitors being located in parallel with a series of the first element and a second element of the second set of elements, the third capacitor of the second set of capacitors being located in parallel with a series of the first element, the second element and a third element of the second set of elements and so on, and

a combination of elements of the stacked elements, parasitic capacitances and compensating capacitors at each node provides a compensated capacitance value for that node, the compensated capacitances values of the nodes being symmetric with respect to a central node of the nodes.

2. The circuit of claim 1, wherein the elements are selected between capacitors, resistors, transistors, diodes and inductors.

3. The circuit of claim 1, wherein the first and second terminals are RF terminals.

4. The circuit of claim 1, wherein the compensating capacitors are located on the side of the stacked elements.

5. The circuit of claim 1, wherein the compensating capacitors are located above the stacked elements.

6. The circuit of claim 1, wherein capacitance values of the compensating capacitors of the first and second set of compensating capacitors are monotonically descending from a largest capacitance value of the first compensating capacitor to a lowest capacitance value of the i-th compensating capacitor.

7. The circuit of claim 6, wherein the compensating capacitors of the first and second set are located above or on the side of the stacked elements, each occupying an area which is monotonically descending from a largest area of the first compensating capacitor to a lowest area of the i-th compensating capacitor.

8. A circuit coupled between a first terminal and a second terminal, comprising:

a plurality of stacked switches, the stacked switches proceeding from a first switch of the stacked switches, closest the first terminal and farthest from the second terminal to an n-th switch of the stacked switches farthest from the first terminal and closest to the second terminal,

a plurality of compensating capacitors associated with the stacked switches,

wherein;

nodes between the switches exhibit parasitic capacitances,

the first terminal is a terminal through which a voltage source is adapted to be coupled to the circuit;

the stacked switches comprise a first set of switches close to the first terminal and far from the second terminal and a second set of switches far from the first terminal and close to the second terminal,

the compensating capacitors comprise a first set of compensating capacitors associated with the first set of switches and a second set of compensating capacitors associated with the second set of switches,

the first set of compensating capacitors comprises i capacitors (i=1, 2, . . . ), the first capacitor of the first set of capacitors being located in parallel with a first switch of the first set of switches, the second capacitor of the first set of capacitors being located in parallel with a series of the first switch and a second switch of the first set of switches, the third capacitor of the first set of capacitors being located in parallel with a series of the first switch, the second switch and a third switch of the first set of switches and so on,

the second set of compensating capacitors comprises i corresponding capacitors (i=1, 2, . . . ), the first capacitor of the second set of capacitors being located in parallel with a first switch of the second set of switches, the second capacitor of the second set of capacitors being located in parallel with a series of the first switch and a second switch of the first set of switches, the third capacitor of the second set of capacitors being located in parallel with a series of the first switch, the second switch and a third switch of the second set of switches and so on, and

a combination of switches of the stacked switches, parasitic capacitances and compensating capacitors at each node provides a compensated capacitance value for that node, the compensated capacitances values of the nodes being symmetric with respect to a central node of the nodes.