Adaptive MOS transistor gate driver and method therefor

• US 9,106,228 B2
• Filed: 04/23/2014
• Issued: 08/11/2015
• Est. Priority Date: 06/23/2013
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Genest, Pierre Andre
• Primary Examiner(s): LUU, AN T
• Application Number:
  US14/259,976
• Publication Number:
  US 20140375376A1
• Time in Patent Office: 475 Days
• Field of Search: 327/108, 327/538, 327540-541, 327/543, 327/544, 363 59- 60
• US Class Current: 1/1
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 2217/0009 AC switches, i.e. delivering AC power to a load
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 2217/009 Resonant driver circuits

Abstract

In an embodiment, a gate driver circuit and/or method therefor may include configuring the gate driver circuit form a drive current to supply to a gate of an MOS transistor wherein the value of the drive current is a minimum value that can be supplied to the gate without increasing a charge stored on a gate-to-source capacitance of the MOS transistor; configuring the gate driver circuit to change the value of the drive current responsively to changes of a Vgs of the MOS transistor.

Claims

1. An adaptive MOS gate driver circuit comprising:

a gate control circuit configured to form a drive signal to drive a gate of an MOS transistor;

a variable frequency oscillator configured to form a clock signal and to adjust a frequency of the clock signal responsively to a difference between a Vgs of the MOS transistor and a first threshold value;

a charge pump circuit configured to provide an output voltage and an output current to the gate control circuit wherein a value of the output current varies proportionally to variations of the frequency of the clock signal; and

the gate control circuit configured to couple the output current from the charge pump circuit to the gate of the MOS transistor responsively to the Vgs of the MOS transistor having a value greater than a second threshold value and to provide a current from a selectively enabled current source of the gate control circuit responsively to the Vgs of the MOS transistor having a value no greater than the second threshold value.

2. The adaptive MOS gate driver circuit of claim 1 wherein the variable frequency oscillator is configured to form the output current from the charge pump circuit to have a minimum value at a minimum frequency of the clock signal wherein the minimum value of the output current from the charge pump circuit is substantially equal to a leakage current of the MOS transistor.

3. The adaptive MOS gate driver circuit of claim 2 wherein the leakage current of the MOS transistor is a leakage current at a minimum value of Vgs that maintains the MOS transistor in state to have drain-to-source current conduction above a drain-to-source leakage current of the MOS transistor.

4. The adaptive MOS gate driver circuit of claim 2 wherein the leakage current of the MOS transistor is a value of current that can be supplied to a gate of the MOS transistor without increasing a value of charge on a gate-to-source capacitance of the MOS transistor.

5. The adaptive MOS gate driver circuit of claim 2 wherein the leakage current of the MOS transistor is a leakage current at a Vgs that is no less than a threshold voltage of the MOS transistor at the value of drain-to-source current that is current conducted by the MOS transistor.

6. The adaptive MOS gate driver circuit of claim 1 wherein the variable frequency oscillator is configured to decrease the frequency of the clock signal responsively to the Vgs of the MOS transistor having a value that is no less than the first threshold value.

7. The adaptive MOS gate driver circuit of claim 1 wherein the variable frequency oscillator is configured to increase the frequency of the clock signal responsively to the Vgs of the MOS transistor having a value that is less than the first threshold value.

8. The adaptive MOS gate driver circuit of claim 1 further including a means for varying the output current to drive the gate of the transistor responsively to the Vgs of the MOS transistor.

9. A method of forming a gate driver circuit for an MOS transistor comprising:

configuring the gate driver circuit to form a first drive current to supply to a gate of an MOS transistor;

configuring the gate driver circuit to change the first drive current to a second drive current in response to a Vgs of the MOS transistor having a value that is no less than a second threshold value; and

configuring the gate driver circuit to change a value of the second drive current responsively to changes of the Vgs for values of the Vgs that are no less than a first threshold value wherein the first threshold value is greater than the second threshold value.

10. The method of claim 9 wherein configuring the gate driver circuit to change the value of the second drive current responsively to changes of a Vgs of the MOS transistor includes configuring the gate driver circuit to decrease the second drive current responsively to an increase in the Vgs and to increase the second drive current responsively to a decrease of the Vgs.

11. The method of claim 10 wherein configuring the gate driver circuit to decrease the second drive current responsively to the increase in the Vgs and to increase the second drive current responsively to the decrease of the Vgs includes configuring the gate driver circuit to decrease the second drive current responsively to the Vgs of the MOS transistor having the value greater than the first threshold value and to increase the drive current responsively to the Vgs of the MOS transistor having the value no greater than the first threshold value.

12. The method of claim 9 further including forming a variable frequency oscillator of the gate driver circuit form a clock signal having a frequency that varies responsively to variations of the Vgs of the MOS transistor.

13. The method of claim 9 wherein configuring the gate driver circuit to form the drive current includes configuring a current source circuit to form the first drive current to supply to the gate of the MOS transistor responsively to the Vgs value less than the second threshold value;

and

configuring the gate driver circuit to terminate the first drive current and form the second drive current to supply to the gate responsively to the Vgs having the value less than the first threshold value and no less than the second threshold value, and to control the value of the second drive current responsively to the value of the Vgs for the Vg values that are no less the first threshold value.

14. A method of forming a gate driver circuit for an MOS transistor comprising:

configuring the gate driver circuit to form a drive current to supply to a gate of an MOS transistor;

configuring the gate driver circuit to change the drive current responsively to a Vgs of the MOS transistor having a value greater than a second threshold value and less than a first threshold value wherein the second threshold value is less than the first threshold value; and

configuring the gate driver circuit to adjust the value of the drive current responsively to the value of the Vgs for Vgs values no less than the first threshold value.

15. The method of claim 14 further including configuring the gate driver circuit to couple a charge pump circuit to form the value of the drive current for the Vgs value greater than the second threshold value but not for the Vgs values less than the second threshold value.

16. The method of claim 15 further including configuring the gate driver circuit to decouple the charge pump circuit from supplying the drive current responsively to the Vgs value less than the second threshold value.

17. The method of claim 15 further including configuring the gate driver circuit to change the value of the drive current after the Vgs has a value no less than the second threshold value.

18. The method of claim 14 wherein configuring the gate driver circuit to adjust the value of the drive current includes configuring the gate driver circuit to change the value of the drive current inversely to the change in the Vgs of the transistor.

19. The method of claim 14 further including configuring the gate driver circuit to form a first drive current to supply to a gate of an MOS transistor for Vgs values less than the second threshold value, and to form a second drive current and change the first drive current to a second drive current to supply to the gate responsively to the Vgs having the value no less than the second threshold value and less than the first threshold value.

20. The method of claim 14 further including configuring a charge pump circuit to form a first voltage;

coupling a current source circuit to receive the first voltage and form the drive current responsively to the Vgs having the value less than the second threshold value; and

configuring the gate driver circuit to couple the charge pump circuit to supply the drive current responsively to the Vgs values no less than the second threshold value.