Programmable interposer circuitry

• US 9,106,229 B1
• Filed: 03/14/2013
• Issued: 08/11/2015
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Hutton, Michael David, Grenier, Richard Arthur
• Primary Examiner(s): Hammond, Crystal L
• Application Number:
  US13/829,965
• Time in Patent Office: 880 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/5382 Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1431 Logic devices
• CPC Class Codes: H01L 2924/1434 Memory
• CPC Class Codes: H01L 2924/15184 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/157 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H03K 19/173 : using elementary logic circuits as components

Abstract

A multichip package that includes a programmable interposer is provided. Multiple integrated circuits may be mounted on the interposer. Active circuitry may also be embedded in the interposer device to facilitate protocol-based communications, debugging, and other desired circuit operations. The interposer device may include programmable interconnect routing circuitry that serves primarily to provide routing for the different circuits within the multichip package. A design tool may be used to design the interposer device. The design tool may include a standard die footprint library from which standard interface templates can be selected when designing an interposer device that has to communicate various on-interposer integrated circuits. The use of standard die footprints may simplify the design of interposers by enabling a family of devices to interface with a given interposer.

Claims

1. An interposer integrated circuit, comprising:

a plurality of input-output pins that interfaces with a plurality of integrated circuits which are mounted on the interposer integrated circuit; and

programmable interconnect circuitry that is coupled to the plurality of input-output pins and that serves to provide routing connections for the plurality of integrated circuits.

2. The interposer integrated circuit defined in claim 1, wherein at least a portion of the plurality input-output pins is coupled to the plurality of integrated circuits via microbumps.

3. The interposer integrated circuit defined in claim 2, wherein at least another portion of the plurality of input-output pins is coupled to flip-chip bumps, and wherein the flip-chip bumps are larger than the microbumps.

4. The interposer integrated circuit defined in claim 1, wherein the programmable interconnect circuitry comprises a plurality of routing paths and a plurality of configurable multiplexing circuits interposed in the plurality of routing paths.

5. The interposer integrated circuit defined in claim 4, further comprising:

a plurality of memory elements that stores configuration data bits for controlling the plurality of configurable multiplexing circuits.

6. The interposer integrated circuit defined in claim 5, further comprising:

a configuration controller that loads the configuration data bits into the plurality of memory elements.

7. The interposer integrated circuit defined in claim 1, wherein the programmable interconnect circuitry includes at least one self-routing path coupled between input-output pins associated with a selected one of the plurality of integrated circuits.

8. The interposer integrated circuit defined in claim 1, further comprising:

active processing circuitry embedded as an integral part of the interposer integrated circuit.

9. The interposer integrated circuit defined in claim 8, wherein the active processing circuitry comprises a debug processor.

10. The interposer integrated circuit defined in claim 8, wherein the active processing circuitry includes an interface circuit configured to implement an input-output communications protocol.

11. A multichip package, comprising:

a package housing;

a plurality of integrated circuits in the package housing; and

a configurable interposer on which the plurality of integrated circuits are mounted, wherein the configurable interposer includes programmable interconnect routing circuitry that serves to perform signal routing for the plurality of integrated circuits.

12. The multichip package defined in claim 11, further comprising:

a package substrate on which the configurable interposer is mounted;

a plurality of flip-chip bumps interposed between the configurable interposer and the package substrate; and

a plurality of microbumps interposed between the configurable interposer and the plurality of integrated circuits.

13. The multichip package defined in claim 11, further comprising:

an additional configurable interposer that is stacked on top of the configurable interposer; and

another plurality of integrated circuits that are mounted on the additional configurable interposer in the package housing.

14. The multichip package defined in claim 11, wherein a given integrated circuit in the plurality of integrated circuits includes logic circuits and debugging circuitry, and wherein the logic circuits generate user signals that are conveyed to the debugging circuitry via at least one signal routing path in the programmable interconnect routing circuitry.

15. The multichip package defined in claim 11, wherein a first integrated circuit in the plurality of integrated circuits includes logic circuits, wherein a second integrated circuit in the plurality of integrated circuits comprises a debug processor, and wherein the logic circuits of the first integrated circuit generate user signals that are conveyed to the debug processor via at least one signal routing path in the programmable interconnect routing circuitry.

16. The multichip package defined in claim 11, wherein a given integrated circuit in the plurality of integrated circuits includes logic circuits, wherein the configurable interposer further includes debug logic embedded as an integral part of the configurable interposer, and wherein the logic circuits in the given integrated circuit generate user signals that are conveyed to the interposer-embedded debug logic via at least one signal routing path in the programmable interconnect routing circuitry.

17. The multichip package defined in claim 11, further comprising:

debug circuitry, wherein a given integrated circuit in the plurality of integrated circuits includes logic circuits that generate test signals that are conveyed to the debug circuitry via a trace buffer.

18. A method for designing a multichip package using a circuit design tool implemented on computing equipment, wherein the multichip package includes a plurality of integrated circuits mounted on an interposer, the method comprising:

receiving a first input from a user that specifies how the plurality of integrated circuits is routed to the interposer;

receiving a second input from the user that specifies input-output pins for the multichip package; and

performing routing connections for the plurality of integrated circuits using programmable interconnect circuitry in the interposer based on the first and second user inputs.

19. The method defined in claim 18, further comprising:

providing the user with an opportunity to select from a library of standard die footprints that serve as an interface between the interposer and the plurality of integrated circuits; and

receiving at least one standard die footprint that is selected by the user.

20. The method defined in claim 18, further comprising:

generating configuration data for configuring the programmable interconnect circuitry so that the programmable interconnect circuitry provides desired routing connections for the plurality of integrated circuits.

21. The method defined in claim 18, further comprising:

receiving additional input from the user that specifies circuits that are embedded within the interposer.