Receive data flow path using a single FEC decoder
First Claim
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1. A receiver comprising:
- a frequency deinterleaver (FDI) coupled to receive data and control information including transmission parameters associated with the data and supply frequency deinterleaved cells corresponding to the data and frequency deinterleaved cells corresponding to the control information;
a time deinterleaver (TDI) to generate forward error correction (FEC) blocks based on the frequency deinterleaved cells;
a forward error correction (FEC) circuit coupled to the time deinterleaver to apply forward error correction to the FEC blocks and coupled to the frequency deinterleaver to apply forward error correction to the control information; and
control logic to control outputs from the frequency deinterleaver and the time deinterleaver to prioritize processing of the control information in the FEC circuit over processing of FEC blocks.
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Abstract
Data flow control in a television receiver controls the output of the frequency deinterleaver (FDI) and the time deinterleaver (TDI) to prioritize processing control information having transmission parameters needed for processing data, thereby facilitating use of one FEC decoder.
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Citations
24 Claims
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1. A receiver comprising:
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a frequency deinterleaver (FDI) coupled to receive data and control information including transmission parameters associated with the data and supply frequency deinterleaved cells corresponding to the data and frequency deinterleaved cells corresponding to the control information; a time deinterleaver (TDI) to generate forward error correction (FEC) blocks based on the frequency deinterleaved cells; a forward error correction (FEC) circuit coupled to the time deinterleaver to apply forward error correction to the FEC blocks and coupled to the frequency deinterleaver to apply forward error correction to the control information; and control logic to control outputs from the frequency deinterleaver and the time deinterleaver to prioritize processing of the control information in the FEC circuit over processing of FEC blocks. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A receiver comprising:
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a frequency deinterleaver (FDI); a time deinterleaver (TDI) coupled to receive data from the FDI and including a time deinterleaver memory; a forward error correction circuit coupled to the time deinterleaver; a dejitter buffer coupled to the forward error correction circuit, the dejitter buffer having a first memory portion for a first data type and a second memory portion for a second data type, wherein the dejitter buffer is configured to monitor the first and second memory portions of the dejitter buffer to supply a control signal to stop output of the time deinterleaver if at least one of the memory portions of the dejitter buffer has an amount of data above a threshold. - View Dependent Claims (14, 15)
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16. A method of processing data and control information in received television signals comprising:
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receiving an indication of a start of a frame that includes the data and control information; stopping output from a time deinterleaver (TDI) of forward error correction (FEC) blocks associated with the data in response to the indication in order to make a forward error correction (FEC) circuit available for processing the control information; sending a request to a frequency deinterleaver to output the control information; and sending a control signal to the time deinterleaver to resume outputting the data when the control information has been processed by the forward error correction circuit to thereby allow the FEC circuit to process the FEC blocks associated with the data. - View Dependent Claims (17, 18, 19)
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20. A method comprising:
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receiving data of a first data type and a second data type from a time deinterleaver at a dejitter buffer memory; monitoring a first portion of the dejitter buffer memory, the first portion for data of the first data type and monitoring a second portion of the dejitter buffer memory, the second portion of the dejitter buffer for data of the second data type; supplying an asserted first control signal to the time deinterleaver to stop upstream generation of data of the first data type if the first portion of the dejitter buffer memory has an amount of data of the first data type above a first threshold, thereby indicating a potential overflow condition; stopping upstream generation of data of the first data type in the time deinterleaver responsive to the asserted first control signal; supplying an asserted second control signal to the time deinterleaver to stop upstream generation of data of the second type if the second portion of the dejitter buffer memory has an amount of data of the second data type that is above a second threshold; and stopping upstream generation of data of the second data type in the time deinterleaver responsive to the asserted second control signal. - View Dependent Claims (21, 22, 23, 24)
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Specification