Hybrid timing recovery for burst mode receiver in passive optical networks

• US 9,106,400 B2
• Filed: 10/23/2012
• Issued: 08/11/2015
• Est. Priority Date: 10/23/2012
• Status: Expired due to Fees

• Current Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Inventors: Cheng, Ning
• Primary Examiner(s): Jaroenchonwanit, Bunjob
• Application Number:
  US13/658,341
• Publication Number:
  US 20140112356A1
• Time in Patent Office: 1,022 Days
• Field of Search: 370/516, 370/517
• US Class Current: 1/1
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/0335 Gardner detector

Abstract

An apparatus for coarse phase alignment of an analog signal comprising: a tapped delay line, a coarse phase alignment logic circuit coupled to the tapped delay line, and a selector coupled to the tapped delay and the coarse phase alignment logic circuit. An apparatus for timing and data recovery for burst mode receivers comprising: a receiver, a coarse phase alignment circuit coupled to the receiver, at least one analog to digital converter (ADC) coupled to the coarse phase alignment circuit such that the coarse phase alignment circuit is positioned between the receiver and the ADC, and a fine phase alignment circuit coupled to the ADC such that the ADC is positioned between the coarse phase alignment circuit and the fine phase alignment circuit, wherein the fine phase alignment circuit produces a recovered data output.

Claims

1. An apparatus for coarse phase alignment of an analog signal comprising:

a tapped delay line configured to output N delayed signals, wherein each delayed signal has a delay based on a bit period, N, and M;

a coarse phase alignment logic circuit coupled to the tapped delay line; and

a selector coupled to the tapped delay line and the coarse phase alignment logic circuit and configured to receive the N delayed signals, wherein N is an integer greater than 1 and M is an integer number of signals output from the apparatus.

2. The apparatus of claim 1, wherein the tapped delay line is coupled to an optical receiver.

3. The apparatus of claim 1, wherein the coarse phase alignment logic circuit is coupled to a clock.

4. The apparatus of claim 1, further comprising a plurality of flip-flops coupled to the tapped delay line such that the flip-flops are positioned between the tapped delay line and the coarse phase alignment logic circuit, and wherein the coarse phase alignment logic circuit is positioned between the flip-flops and the selector.

5. The apparatus of claim 4, wherein from 2 to 16 flip-flops are positioned between the tapped delay line and the coarse phase alignment logic circuit.

6. The apparatus of claim 5, wherein four flip-flops are positioned between the tapped delay line and the coarse phase alignment logic circuit.

7. A method of burst mode clock and data recovery at an Optical Line Terminal (OLT) in a Passive Optical Network (PON), the method comprising:

receiving an upstream analog signal;

aligning a coarse phase for the upstream analog signal using a fractional delay circuit to create at least one coarse phase aligned analog signal, wherein the aligning comprises creating, from the upstream analog signal, N delayed signals, wherein each delayed signal has a delay based on a bit period, N, and M, wherein N is an integer number of first desired signals output to a selector, and wherein M is an integer number of second desired signals output to at least one analog-to-digital converter (ADC);

converting the at least one coarse phase aligned analog signal to at least one digital signal;

aligning a fine phase for the at least one digital signal to create a fine phase aligned signal; and

outputting a recovered data signal based on the fine phase aligned signal.

8. The method of claim 7, wherein the aligning further comprises:

comparing fractionally delayed versions of the upstream analog signal to a system clock; and

selecting a single fractionally delayed version of the upstream signal for usage in data recovery.

9. The method of claim 7, wherein converting is accomplished by the at least one ADC running at a nominal bit rate.

10. The method of claim 7, wherein the method is accomplished in less than a 44 bit period.

11. The method of claim 7, wherein M is less than N.

12. The method of claim 11, wherein M is 1.

13. An apparatus for timing and data recovery for burst mode receivers comprising:

a receiver;

a coarse phase alignment logic circuit coupled to the receiver and comprising;

a tapped delay line coupled to the receiver;

a plurality of flip-flops coupled to the tapped delay line such that the tapped delay line is positioned between the receiver and the flip-flops, wherein the flip-flops are further coupled to a clock;

a coarse phase alignment logic circuit coupled to the flip-flops such that the flip-flops are positioned between the tapped delay line and the coarse phase alignment logic circuit; and

a selector directly connected to the tapped delay line and coupled to the coarse phase alignment logic circuit, wherein the coarse phase alignment logic circuit is positioned between the flip-flops and the selector, wherein the tapped delay line is positioned between the receiver and the selector;

an analog-to-digital converter (ADC) coupled to the coarse phase alignment logic circuit such that the coarse phase alignment logic circuit is positioned between the receiver and the ADC; and

a fine phase alignment circuit coupled to the ADC such that the ADC is positioned between the coarse phase alignment logic circuit and the fine phase alignment circuit, wherein the fine phase alignment circuit is configured to produce a recovered data output.

14. The apparatus of claim 13, wherein the tapped delay line has from 2 to 16 taps.

15. The apparatus of claim 13, wherein the fine phase alignment logic circuit comprises:

an interpolator coupled to the ADC such that the ADC is positioned between the coarse phase alignment logic circuit and the interpolator;

a timing error estimator coupled to the interpolator such that the interpolator is positioned between the timing error estimator and the ADC; and

a loop filter coupled to the interpolator and the timing error estimator such that the loop filter is positioned between the interpolator and the timing error estimator.

16. The apparatus of claim 15 further comprising a comparator coupled to the interpolator such that the interpolator is positioned between the comparator and the ADC, wherein the timing error estimator is positioned between the comparator and the loop filter.

17. The apparatus of claim 13, wherein the fine phase alignment logic circuit comprises:

a phase shifter coupled to the clock and to the ADC, wherein the phase shifter is positioned between the clock and the ADC, and wherein the phase shifter is not directly connected to the coarse phase alignment logic circuit; and

a timing error estimator coupled to the phase shifter and the ADC.

18. The apparatus of claim 17 further comprising a comparator coupled to the ADC and the timing error estimator, wherein the ADC is positioned between the comparator and the selector, and wherein the timing error estimator is positioned between the comparator and the phase shifter.

19. The apparatus of claim 18, wherein the fine phase alignment circuit is configured to use a Mueller-Muller algorithm or a Gardner algorithm for timing error estimation.