Signal delay estimator with absolute delay amount and direction estimation

• US 9,106,402 B2
• Filed: 06/23/2014
• Issued: 08/11/2015
• Est. Priority Date: 12/27/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Deutschland GmbH (Intel Corporation)
• Inventors: Belitzer, Alexander
• Primary Examiner(s): LEE, SIU M
• Application Number:
  US14/312,024
• Publication Number:
  US 20140301514A1
• Time in Patent Office: 414 Days
• US Class Current: 1/1
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H04B 17/104 of other parameters, e.g. DC offset, delay or propagation times
• CPC Class Codes: H04L 7/0033 Correction by delay
• CPC Class Codes: H04L 7/0041 Delay of data signal
• CPC Class Codes: H04L 7/0079 Receiver details
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A signal delay estimator includes an adjustable delay element for delaying a first signal to obtain a delayed first signal, a delay amount estimator for estimating a delay amount between the delayed first signal and a second signal that is similar and delayed relative to the first signal, and a leading signal determiner for determining whether the delayed first signal leads the second signal or vice versa, and for generating a corresponding binary signal. A selective inverter is provided for selectively inverting the delay amount depending on the binary signal. The signal delay estimator also includes a feedback element to the adjustable delay element for controlling a delay based on an output of the selective inverter. Another exemplary signal delay estimator includes a closed control loop with an adjustable delay element and separate first and second processing paths for absolute delay amount and delay direction, respectively.

Claims

1. A signal delay estimator, comprising:

an adjustable delay element for delaying a first signal to obtain a delayed first signal;

a delay amount estimator configured to estimate a delay amount between the delayed first signal and a second signal that is similar and delayed relative to the first signal;

a leading signal determiner configured to determine whether the delayed first signal leads the second signal or vice versa, and generate a corresponding indication signal based thereon; and

a feedback element to the adjustable delay element configured to control a delay of the adjustable delay element based on the delay amount and the indication signal.

2. The signal delay estimator according to claim 1, wherein the leading signal determiner comprises:

a first input configured to receive an error signal corresponding to a delay between the delayed first signal and the second signal;

a second input configured to receive the second signal;

a slope detector configured to detect whether one of the first signal and the second signal has a slope greater than zero, and output, as a slope detector output signal, the error signal if the slope is greater than zero and otherwise output a zero signal;

an error integrator configured to integrate the slope detector output signal; and

an integration result evaluator configured to set the corresponding indication signal, indicating if an integration result is positive or negative.

3. The signal delay estimator according to claim 2, wherein the error integrator is configured to integrate the slope detector output signal over a time interval.

4. The signal delay estimator according to claim 3, wherein the time interval is variable, and wherein the signal delay estimator further comprises a time interval adjuster configured to set a relatively short time interval if a bandwidth of the first signal is greater than a threshold and a relatively long time interval if the bandwidth of the first signal is less than the threshold.

5. The signal delay estimator according to claim 2, wherein at least one of the error signal and the slope detector output signal is a time discrete signal, and wherein the error integrator is configured to sum the slope detector output signal over a plurality of samples.

6. The signal delay estimator according to claim 1, wherein the leading signal determiner comprises:

a first input configured to receive an error signal corresponding to a delay between the delayed first signal and the second signal;

a second input configured to receive the second signal;

a slope detector configured to detect whether one of the first signal and the second signal has a slope less than zero, and output, as a slope detector output signal, the error signal if the slope is less than zero and otherwise output a zero signal;

an error integrator configured to integrate the slope detector output signal; and

an integration result evaluator configured to set the corresponding indication signal, indicating if an integration result is positive or negative.

7. The signal delay estimator according to claim 1, wherein the delay amount estimator comprises:

an error signal determiner configured to determine an error signal corresponding to a delay between the delayed first signal and the second signal; and

a value error integrator configured to integrate a value of the error signal over a value integration time interval, wherein the value error integrator outputs the delay amount.

8. The signal delay estimator according to claim 7, wherein the error signal determiner of the delay amount estimator comprises an output configured to provide the error signal to the leading signal determiner.

9. The signal delay estimator according to claim 1, further comprising at least one DC remover configured to remove a DC component of at least one of the first signal and the second signal.

10. The signal delay estimator according to claim 1, wherein the adjustable delay element comprises an integer delay portion and a fractional delay portion relative to a sampling rate of the first and second signals.

11. A mobile communication device, comprising:

an antenna port;

a digital baseband processor;

an analog-frontend coupled to the antenna port and to the digital baseband processor; and

a signal delay estimator associated with the digital baseband processor and the analog-frontend, comprising;

an adjustable delay element configured to delay a first signal to obtain a delayed first signal;

a delay amount estimator configured to estimate a delay amount between the delayed first signal and a second signal that is similar and delayed relative to the first signal;

a leading signal determiner configured to determine whether the delayed first signal leads the second signal or vice versa, and generate a corresponding indication signal; and

a feedback element to the adjustable delay element configured to control a delay based on the delay amount and the indication signal.

12. The mobile communication device according to claim 11, wherein the first signal is provided by the digital baseband processor and the second signal is provided by the analog-frontend to the antenna port based on the first signal.

13. A method for estimating a delay between a first signal and a similar second signal, the method comprising:

delaying the first signal by an adjustable delay to obtain a delayed first signal;

estimating a delay amount between the delayed first signal and the second signal;

determining whether the delayed first signal leads the second signal or vice versa and generating a corresponding indication signal based thereon; and

adjusting the adjustable delay used for delaying the first signal based on the estimated delay amount and the indication signal.

14. The method according to claim 13, wherein determining whether the delayed first signal leads the second signal or vice versa comprises:

detecting whether one of the delayed first signal and the second signal has a slope greater than zero;

determining an error signal between the delayed first signal and the second signal;

generating a slope detection signal if the slope is greater than zero and otherwise a zero signal;

integrating the error signal if the slope is greater than zero; and

setting the indication, depending on whether an integration result is positive or negative.

15. The method according to claim 14, wherein the error signal is integrated over a time interval and then evaluated as to whether the integration result is positive or negative.

16. The method according to claim 15, further comprising:

setting a relatively short time interval as the time interval if a bandwidth of the first signal is greater than a threshold and setting a relatively long time interval as the time interval if the bandwidth of the first signal is less than the threshold.

17. The method according to claim 14, wherein at least one of the error signal and the slope detection signal is a time discrete signal, and wherein integrating the error signal comprises summing the error signal over a plurality of samples.

18. The method according to claim 13, further comprising:

setting a loop gain based on one of a decreasing loop gain and an estimation of a noise portion within the delay amount; and

scaling the conditionally inverted delay amount with the loop gain.

19. A transmitter path, comprising:

an analog signal generator configured to receive an input transmit signal;

an amplifier coupled to an output of the analog signal generator and configured to generate an output transmit signal;

a delay tracking loop configured to estimate a delay between the input transmit signal and the output transmit signal;

an evaluation circuit configured to output an adjustment signal to adjust one or more parameters of the analog signal generator or the amplifier based on a comparison of the input transmit signal and the output transmit signal according to the estimated delay.

20. The transmitter path of claim 19, wherein the adjustment signal comprises a supply voltage adjustment signal configured to modify a supply voltage of the amplifier.

21. The transmitter path of claim 19, wherein the adjustment signal comprises a bias condition adjustment signal configured to modify a bias voltage of the amplifier.

22. The transmitter path of claim 19, wherein the analog signal generator further comprises a mixer arrangement configured to receive the input transmit signal and provide an output signal to the amplifier.