Solid-state image pickup device with plurality of converters

• US 9,106,859 B2
• Filed: 10/26/2012
• Issued: 08/11/2015
• Est. Priority Date: 11/04/2011
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kizuna, Shunsuke, Dosaka, Katsumi, Utsunomiya, Hiroto
• Primary Examiner(s): Chavez, Renee D
• Application Number:
  US13/661,724
• Publication Number:
  US 20130112852A1
• Time in Patent Office: 1,019 Days
• Field of Search: 250/208.1, 348294-324
• US Class Current: 1/1
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

A solid-state image pickup device includes a column ADC realizing higher precision and higher-speed conversion. Converters converts a signal of each pixels output via a corresponding vertical read line to a digital value by sequentially executing first to N-th (N: integer of three or larger) conversion stages. In the first to (N−1)th conversion stages, each converter determines a value of upper bits including the most significant bit of a digital value by comparing the voltage at a retention stage with a reference voltage while changing the voltage at a retention node. In the N-th conversion stage, each converter determines a value of remaining bits to the least significant bit by comparing the voltage at the retention node with the reference voltage while continuously changing the voltage at the retention node in a range of the voltage step in the (N−1)th conversion stage or a range exceeding the range.

Claims

1. A solid-state image pickup device comprising:

an imaging unit in which a plurality of pixels each including a photoelectric conversion element for converting a light signal to an electric signal are disposed in a matrix, and signals of pixels in a selected row are output via a plurality of vertical read lines disposed for columns while sequentially scanning the pixels row by row; and

a plurality of converters provided in correspondence with the vertical read lines,

wherein each of the converters has a retention node for retaining a signal of a pixel which is output via a corresponding vertical read line and converts the signal retained by the retention node to a digital value by sequentially executing first to N-th (N;

integer of three or larger) conversion stages,

wherein, in the first conversion stage, each of the converters determines a value of one or plural upper bits including the most significant bit of the digital value by comparing the voltage at the retention node with a reference voltage while changing the voltage at the retention node by a predetermined voltage step,

wherein, in the i-th conversion stage (2≦

i≦

N−

1), each of the converters determines a value of one or plural bits subsequent to the bit determined in the (i−

1)th stage by comparing the voltage at the retention node with the reference voltage while changing the voltage at the retention node by a voltage step smaller than the voltage step in the (i−

1)th conversion stage, and

wherein, in the N-th conversion stage, each of the converters determines a value of bits subsequent to the bit determined in the (N−

1)th conversion stage to the least significant bit by comparing the voltage at the retention node with the reference voltage while continuously changing the voltage at the retention node in a range of the voltage step in the (N−

1)th conversion stage or a range obtained by adding an overrange to the range,

wherein each of the converters includes;

a plurality of capacitive elements each having a first electrode coupled to the retention node and each corresponding to any one of the first to (N−

1)th conversion stages;

a comparator comparing the voltage at the retention node with the reference voltage; and

a voltage applying unit applying variable voltage to a second electrode of each of the capacitive elements coupled to the retention node,

wherein a plurality of capacitive elements coupled to the retention node include first to M-th (M;

integer of two or larger) capacitive elements corresponding to the (N−

1) conversion stage,

wherein the voltage applying unit includes;

a first power supply node to which a first voltage is applied;

a second power supply node to which a second voltage is applied;

a third power supply node which is switchably connected to one of the second voltage applied in the first to (N−

1)th conversion stages, or the slope voltage which changes continuously in a first range from the first voltage to the second voltage or a second range exceeding the first range.

2. The solid-state image pickup device according to claim 1,

wherein, during execution of the j-th conversion stage (1≦

j≦

N−

2) in the first to (N−

2)th conversion stages, the voltage applying unit changes the voltage at the retention node by a predetermined voltage step by performing single-element switching of switching a voltage applied to the capacitive element corresponding to the j-th conversion stage element by element and/or plural-element switching of switching a voltage applied to the capacitive elements corresponding to the (j+1)th to (N−

1)th conversion stages by plural elements until the logic level of an output signal of the comparator is inverted, and

wherein, in the (N−

1)th conversion stage, the voltage applying unit changes the voltage at the retention node by a predetermined voltage step by performing the single-element switching of switching the voltage applied to the capacitive element corresponding to the (N−

1)th conversion stage element by element until the logic level of the output signal of the comparator is inverted.

3. The solid-state image pickup device according to claim 2, wherein in the N-th conversion stage, the voltage applying unit continuously changes the voltage at the retention node by applying slope voltage which continuously changes to the second electrode of the capacitive element to which the application voltage is switched at the end of the (N−

1)th conversion stage.

4. The solid-state image pickup device according to claim 3,

wherein the voltage applying unit includes:

first to M-th intermediate nodes provided in correspondence with the first to M-th (M;

integer of two or larger) capacitive elements;

first to M-th change-over switches corresponding to the first to M-th capacitive elements and also the first to M-th intermediate nodes, respectively, and each for switching a connection destination of the second electrode of a corresponding capacitive element from the first power supply node to a corresponding intermediate node; and

first to (M−

1)th interlocking switches corresponding to the second to M-th change-over switches and also corresponding to the first to (M−

1)th intermediate nodes, and each for switching the connection destination of a corresponding intermediate node from the third power supply node to the second power supply node interlockingly with the switching of a corresponding change-over switch,

wherein, in the (N−

1)th conversion stage, at least a part of the first to M-th change-over switches is sequentially switched in order from the first to the M-th number until logic level of an output signal of the comparator is inverted, and

wherein, in the N-th conversion stage, the voltage of the third power supply node changes in a slope shape, and the slope voltage is applied to a second electrode of a capacitive element coupled to the change-over switch which is switched at the end of the (N−

1)th conversion stage.

5. The solid-state image pickup device according to claim 2,

wherein the retention node is coupled to a first input terminal of the comparator,

wherein each of the converters further includes a capacitive element coupled between a second input terminal of the comparator and a ground node, and

wherein the capacitive element coupled to the second input terminal of the comparator holds, as the reference voltage, a signal captured by the retention node in astute where the pixels are not irradiated with light.

6. A solid-state image pickup device comprising:

an imaging unit in which a plurality of pixels each including a photoelectric conversion element for converting a light signal to an electric signal are disposed in a matrix, and signals of pixels in a selected row are output via a plurality of vertical read lines disposed for columns while sequentially scanning the pixels row by row; and

a plurality of converters provided in correspondence with the vertical read lines,

wherein each of the converters has a retention node for retaining a signal of a pixel which is output via a corresponding vertical read line and converts the signal retained by the retention node to a digital value by sequentially executing first to N-th (N;

integer of three or larger) conversion stages,

wherein, in the first conversion stage, each of the converters determines a value of one or plural upper bits including the most significant bit of the digital value by comparing the voltage at the retention node with a reference voltage while changing the voltage at the retention node by a predetermined voltage step,

wherein, in the i-th conversion stage (2≦

i≦

N−

1), each of the converters determines a value of one or plural bits subsequent to the bit determined in the (i−

1)th stage by comparing the voltage at the retention node with the reference voltage while changing the voltage at the retention node by a voltage step smaller than the voltage step in the (i−

1)th conversion stage, and

wherein, in the N-th conversion stage, each of the converters determines a value of bits subsequent to the bit determined in the (N−

1)th conversion stage to the least significant bit by comparing the voltage at the retention node with the reference voltage while continuously changing the voltage at the retention node in a range of the voltage step in the (N−

1)th conversion stage or a range obtained by adding an overrange to the range,

wherein each of the converters includes;

a plurality of capacitive elements each having a first electrode coupled to the retention node and each corresponding to any one of the first to (N−

1)th conversion stages;

a comparator comparing the voltage at the retention node with the reference voltage; and

a voltage applying unit applying variable voltage to a second electrode of each of the capacitive elements coupled to the retention node,

wherein a plurality of capacitive elements coupled to the retention node include first to M-th (M;

integer of two or larger) capacitive elements corresponding to the (N−

1) conversion stage,

wherein the voltage applying unit includes;

a first power supply node to which a first voltage is applied;

a second power supply node to which a second voltage is applied;

a third power supply node which is switchably connected to one of the second voltage applied in the first to (N−

1)th conversion stages, or the slope voltage which changes continuously in a first range from the first voltage to the second voltage or a second range exceeding the first range;

first to M-th intermediate nodes provided in correspondence with the first to M-th (M;

integer of two or larger) capacitive elements;

first to M-th change-over switches corresponding to the first to M-th capacitive elements and also the first to M-th intermediate nodes, respectively, and each for switching a connection destination of the second electrode of a corresponding capacitive element from the first power supply node to a corresponding intermediate node; and

first to (M−

1)th interlocking switches corresponding to the second to M-th change-over switches and also corresponding to the first to (M−

1)th intermediate nodes, and each for switching the connection destination of a corresponding intermediate node from the third power supply node to the second power supply node interlockingly with the switching of a corresponding change-over switch,

wherein the voltage applying unit further includes;

first to (M−

1)th dummy nodes disposed in positions close to the first to (M−

1)th intermediate nodes, respectively; and

first to (M−

1)th dummy switches corresponding to the second to M-th change-over switches, respectively, and corresponding to the first to M-th dummy nodes, and each switching connection destination of a corresponding dummy node from the second power supply node to the third power supply node interlockingly with the switching of the corresponding change-over switch.