Electric charge flow circuit for a time measurement

• US 9,110,116 B2
• Filed: 09/23/2014
• Issued: 08/18/2015
• Est. Priority Date: 10/06/2011
• Status: Active Grant

• Current Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Inventors: La Rosa, Francesco, Fornara, Pascal
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US14/494,095
• Publication Number:
  US 20150043269A1
• Time in Patent Office: 329 Days
• Field of Search: 257/48, 257314-324
• US Class Current: 1/1
• CPC Class Codes: G01R 17/02 Arrangements in which the value to be measured is automatically compared with a reference value
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: G04F 10/10 by measuring electric or magnetic quantities changing in proportion to time
• CPC Class Codes: G04F 13/00 Apparatus for measuring unknown time intervals by means not provided for in groups G04F5/00 - G04F10/00
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: H01G 4/005 Electrodes
• CPC Class Codes: H01G 4/018 Dielectrics
• CPC Class Codes: H01G 4/38 Multiple capacitors, i.e. structural combinations of fixed capacitors
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A charge flow circuit for a time measurement, including a plurality of elementary capacitive elements electrically in series, each elementary capacitive element leaking through its dielectric space.

Claims

1. A circuit, comprising:

a capacitive charge storage element having a first electrode connected to a floating node and a second electrode connected to a first voltage node; and

a charge flow circuit connected to the floating node, the charge flow circuit comprising a plurality of capacitive elements connected in series between the floating node and a second voltage node,

wherein the capacitive charge storage element has a larger charge retention capacitance than the charge flow circuit.

2. The circuit of claim 1, wherein each of the capacitive elements of the charge flow circuit comprises a first electrode, a dielectric layer and a second electrode, said dielectric layer including a first region and a second region, wherein the first region operates by tunnel effect.

3. The circuit of claim 2, wherein the first region of the dielectric layer has a smaller thickness than the second region.

4. The circuit of claim 1, further comprising a capacitive initialization element connected to the floating node.

5. The circuit of claim 4, wherein the capacitive initialization element has a charge retention capacitance greater than the charge flow circuit but smaller than the capacitive charge storage element.

6. The circuit of claim 2, wherein the first and second electrodes are formed in conductive levels of an integrated circuit and the dielectric layer is formed in a dielectric level of the integrated circuit.

7. The circuit of claim 1, wherein each of the capacitive elements in series connection within the charge flow circuit is configured to leak charge by tunneling effect.

8. A circuit, comprising:

a capacitive charge storage element having a first electrode connected to a floating node;

a charge flow circuit connected to the floating node, the charge flow circuit comprising a plurality of series-connected capacitive elements,

wherein the capacitive charge storage element has a larger charge retention capacitance than the charge flow circuit; and

a comparator connected to each node connected to two successive ones of the series-connected capacitive elements of the charge flow circuit,

wherein each comparator is configured to compare the voltage of the respective node with a threshold value.

9. The circuit of claim 8, wherein each of the series-connected capacitive elements of the charge flow circuit comprises a first electrode, a dielectric layer and a second electrode.

10. The circuit of claim 9, wherein said dielectric layer includes a first region and a second region, wherein the first region is configured to leak charge by tunnel effect.

11. The circuit of claim 10, wherein the first region of the dielectric layer has a smaller thickness than the second region.

12. The circuit of claim 9, wherein the first and second electrodes are formed in conductive levels of an integrated circuit and the dielectric layer is formed in a dielectric level of the integrated circuit.

13. The circuit of claim 9, wherein said first and second electrodes are made of polysilicon.

14. The circuit of claim 9, wherein said first electrodes are regions of a semiconductor substrate, and said second electrodes are made of polysilicon.

15. A circuit, comprising:

a capacitive charge storage element having a first electrode connected to a floating node; and

a charge flow circuit connected to the floating node, the charge flow circuit comprising a plurality of elementary capacitive elements electrically in series, each elementary capacitive element leaking through its dielectric space, wherein each elementary capacitive element is formed by a stack of a first electrode, a dielectric layer and a second electrode, wherein the dielectric layer is configured to permit charge flow by tunnel effect.

16. The circuit of claim 15, wherein said dielectric layer includes at least one region configured for letting charges flow by tunnel effect.

17. The circuit of claim 15, wherein said first electrodes are formed in a same first conductive or semiconductor level of an integrated circuit chip, and wherein said second electrodes are formed in a same second conductive level of the chip.

18. The circuit of claim 17, wherein said dielectric layer comprises an oxide-nitride-oxide stack, and wherein said dielectric layer includes at least one region configured for letting charges flow by tunnel effects, said at least one region being made of silicon oxide.

19. The circuit of claim 15, wherein said first and second electrodes are made of polysilicon.

20. The circuit of claim 15, wherein said first electrodes are regions of a semiconductor substrate, and said second electrodes are made of polysilicon.

21. The circuit of claim 15, wherein each elementary capacitive element has a capacitance ranging between 1*10⁻

15 and 5*10<sup>−

15</sup> farads.

22. The circuit of claim 15, wherein the capacitive charge storage element has a capacitance ranging between 10*10⁻

12 and 100*10<sup>−

12</sup> farads.

23. The circuit of claim 15, further comprising a capacitive initialization element connected to a floating node common to the capacitive charge storage element and to the charge flow circuit.

24. The circuit of claim 23, wherein the capacitive initialization element has a capacitance ranging between 10*10⁻

15 and 100*10<sup>−

15</sup> farads.

25. The circuit of claim 15, further comprising a device configured to measure the residual charge of the capacitive charge storage element, said device comprising, connected to each node common to two successive capacitive elements of the charge flow circuit, a comparator configured for comparing the voltage of said node with a threshold.

26. The circuit of claim 15, further comprising non-volatile memory cells and logic blocks comprising MOS transistors supported by a semiconductor substrate which also supports the capacitive charge storage element and the charge flow circuit.