Microarchitecture for floating point fused multiply-add with exponent scaling

• US 9,110,713 B2
• Filed: 08/30/2012
• Issued: 08/18/2015
• Est. Priority Date: 08/30/2012
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Wang, Liang-Kai
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US13/598,760
• Publication Number:
  US 20140067895A1
• Time in Patent Office: 1,083 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00

Abstract

Systems and methods for implementing a floating point fused multiply and accumulate with scaling (FMASc) operation. A floating point unit receives input multiplier, multiplicand, addend, and scaling factor operands. A multiplier block is configured to multiply mantissas of the multiplier and multiplicand to generate an intermediate product. Alignment logic is configured to pre-align the addend with the intermediate product based on the scaling factor and exponents of the addend, multiplier, and multiplicand, and accumulation logic is configured to add or subtract a mantissa of the pre-aligned addend with the intermediate product to obtain a result of the floating point unit. Normalization and rounding are performed on the result, avoiding rounding during intermediate stages.

Claims

1. A method of implementing a floating point scaled fused multiply and accumulate (FMASc) operation in a floating point unit, the method comprising:

multiplying mantissas of a floating point multiplier operand with a floating point multiplicand operand in a multiplier block to obtain a mantissa of a product;

determining a count of the number of leading zeros (LZC) of the mantissa of a floating point addend operand in a LZC block;

determining a pre-alignment shift value for the floating point addend operand based on the LZC, a scaling factor operand, and exponents of the floating point addend operand, the floating point multiplier operand, and the floating point multiplicand operand in a pre-alignment block;

shifting the mantissa of the floating point addend operand with the pre-alignment shift value to obtain a pre-aligned addend in an alignment block;

accumulating the mantissa of the product and the pre-aligned addend to obtain an intermediate result in an accumulator block;

determining the number of leading zeros of the intermediate result in a leading zero anticipator block;

determining a normalizing shift value based on the pre-alignment shift value and the number of leading zeros of the intermediate result; and

normalizing the intermediate result based on the normalizing shift value in a normalization block to obtain a normalized output of the FMASc operation.

2. The method of claim 1 further comprising rounding the normalized output with a rounding value based on the normalizing shift value.

3. The method of claim 2, wherein the normalizing shift value is one of a left shift or a right shift.

4. The method of claim 3, wherein the left shift is based on the number of leading zeros of the intermediate result or a function of exponents of the floating point addend operand, the floating point multiplier operand, and the floating point multiplicand operand.

5. The method of claim 3, wherein the right shift is based on a function of the scaling factor operand, and exponents of the floating point addend operand, the floating point multiplier operand, and the floating point multiplicand operand.

6. The method of claim 1, wherein the accumulating is one of an adding or subtracting, as specified by the FMASc operation.

7. A method of executing a floating point operation in a floating point unit, the method comprising:

receiving multiplier, multiplicand, addend, and scaling factor operands in the floating point unit;

performing a partial multiplication operation on mantissas of the multiplier and multiplicand operand in a multiplier block to obtain an intermediate product;

pre-aligning a mantissa of the addend with the intermediate product based on the scaling factor and exponents of the addend, multiplier, and multiplicand in a pre-alignment block; and

accumulating the mantissa of the pre-aligned addend and the intermediate product in an accumulator block to obtain the result of the floating point operation.

8. The method of claim 7, further comprising normalizing the result.

9. The method of claim 8, further comprising performing a rounding operation on the normalized result, wherein rounding is avoided in the method, before the normalized result is obtained.

10. The method of claim 7, wherein the accumulating is one of an adding or subtracting, as specified by the floating point operation.

11. A floating point unit comprising:

input multiplier, multiplicand, addend, and scaling factor operands;

a multiplier block configured to multiply mantissas of the multiplier and multiplicand to generate an intermediate product;

alignment logic configured to pre-align the addend with the intermediate product based on the scaling factor and exponents of the addend, multiplier, and multiplicand; and

accumulation logic configured to add or subtract a mantissa of the pre-aligned addend with the intermediate product to obtain a result of the floating point unit.

12. The floating point unit of claim 11, further comprising a normalization block configured to normalize the result.

13. The floating point unit of claim 12, further comprising a leading zero anticipator (LZA) block configured to anticipate the number of leading zeros in the result based on an intermediate result from the accumulation logic, such that the normalization is based on an output of the LZA block.

14. The floating point unit of claim 12, further comprising a rounding block configured to perform a specified rounding on the normalized result.

15. The floating point unit of claim 11, wherein the mantissa of the addend is divided into a high part and a low part, such that the alignment logic is configured to separately pre-align the low part and the high part, wherein the pre-aligned low part is used for addition with the intermediate product in the addition logic, and an incrementer logic is configured to increment or decrement the high part based on a carry or borrow value from the output of the addition logic.

16. The floating point unit of claim 11, wherein the multiplier block is configured as a Booth multiplier.

17. The floating point unit of claim 11, wherein the intermediate product is represented in a redundant format comprising a sum part and a carry part.

18. The floating point unit of claim 11, configured to execute a floating point fused multiply and add with scaling (FMASc) instruction.

19. The floating point unit of claim 11 integrated in at least one semiconductor die.

20. The floating point unit of claim 11 integrated into a device selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer.

21. A processing system comprising:

means for receiving floating point multiplier, multiplicand, addend, and scaling factor operands;

multiplier means for multiplying mantissas of the multiplier and multiplicand to generate an intermediate product;

alignment means for pre-aligning the addend with the intermediate product based on the scaling factor and exponents of the addend, multiplier, and multiplicand; and

accumulation means for adding or subtracting a mantissa of the pre-aligned addend with the intermediate product to obtain a floating point result of the processing system.

22. The processing system of claim 21, further comprising a normalization means for normalizing the floating point result.

23. The processing system of claim 21, further comprising means for rounding the normalized floating point result based on a specified rounding mode.

24. The processing system of claim 21, configured to execute a floating point fused multiply and add with scaling (FMASc) instruction.

25. A method of performing a dual data path floating point fused multiply and accumulate operation with scaling (FMASc) operation in a floating point unit, the method comprising:

receiving multiplier, multiplicand, addend, and scaling factor operands in a multiplier block;

performing a partial multiplication operation on mantissas of the multiplier and multiplicand operand in the multiplier block to obtain an intermediate product;

separating the mantissa of the addend into a high addend part with more significant bits and a low addend part with less significant bits;

aligning the high addend part to form an incrementer part;

aligning the low addend part with the intermediate product;

accumulating the low addend part with the intermediate product in an accumulator block to form an add part;

incrementing or decrementing the incrementer part based on a carry out or borrow value respectively from the add part to form a final incrementer part; and

concatenating the final incrementer part with the add part to form the result of the floating point operation.

26. The method of claim 25, wherein aligning the high and low addend parts are based on the value of the scaling factor, and a difference between exponents of the addend operand and the sum of the exponents of the multiplier and multiplicand operands.

27. The method of claim 26, wherein if the scaling factor is zero, left and right shift values for aligning the high and low addend parts are determined based on the difference between exponents of the addend operand and the sum of the exponents of the multiplier and multiplicand operands being one of greater than, equal to, or less than a first constant.

28. The method of claim 26, wherein if the scaling factor is not equal to zero, left and right shift values for aligning the high and low addend parts are determined based on the difference between exponents of the addend operand and the sum of the exponents of the multiplier and multiplicand operands being one of greater than, equal to, or less than a second constant.

29. The method of claim 26, wherein shift values for aligning the high and low addend parts where the accumulating specified in the FMASc operation relates to subtraction of the addend from the product of the multiplier and multiplicand operands are different from shift values for aligning the high and low addend parts where the accumulating specified in the FMASc operation relates to addition of the addend with the product of the multiplier and multiplicand operands.