System and methods for dynamic management of hardware resources

• US 9,111,059 B2
• Filed: 11/01/2013
• Issued: 08/18/2015
• Est. Priority Date: 11/01/2012
• Status: Active Grant

• Current Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Original Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Inventors: Pattichis, Marios Stephanou, Jiang, Yuebing, Llamocca Obregon, Daniel Rolando
• Primary Examiner(s): NGUYEN, NHA T
• Application Number:
  US14/069,822
• Publication Number:
  US 20140165021A1
• Time in Patent Office: 655 Days
• Field of Search: 716/116, 716/117, 716/132, 716/133
• US Class Current: 1/1
• CPC Class Codes: G06F 2111/06 Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: H03H 17/0241 Distributed arithmetic
• CPC Class Codes: H03H 17/0294 Variable filters; Programmable filters
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H04N 19/625 using discrete cosine transform [DCT]

Abstract

A dynamically reconfigurable framework manages processing applications in order to meet time-varying constraints to select an optimal hardware architecture. The optimal architecture satisfies time-varying constraints including for example, supplied power, required performance, accuracy levels, available bandwidth, and quality of output such as image reconstruction. The process of determining an optimal solution is defined in terms of multi-objective optimization using Pareto-optimal realizations.

Claims

1. A computer system including a processor, a memory, and a field programmable gate array for producing a dynamically reconfigurable framework for performing a task comprising the steps of:

varying by the processor one or more hardware parameters to generate a plurality of hardware realizations, each hardware realization associated with one or more power measurements, performance measurements and accuracy measurements;

obtaining by the processor one or more objectives for each hardware realization to obtain hardware objectives, wherein the hardware objectives consist of a power value, an energy value, a performance value, a bitrate value, and an accuracy value;

using the hardware objectives by the processor in real-time to determine the hardware realizations of the plurality that are Pareto-optimal to obtain a collection of Pareto-optimal hardware realizations;

storing in memory the collection of Pareto-optimal hardware realizations and the hardware objectives;

selecting by the processor in real-time one or more Pareto-optimal hardware realizations from the plurality that meet or exceed one or more time-varying constraints; and

programming the field programmable gate array in real-time with the one or more Pareto-optimal hardware realizations, wherein the programming step further comprises the step of using by the processor one or more selected from the group comprising of;

a dynamic partial reconfiguration and a dynamic frequency control.

2. The computer system according to claim 1, wherein the one or more hardware parameters include frequency of operation.

3. The computer system according to claim 1, wherein the one or more time-varying constraints are selected from the group consisting of:

a minimum power value, a minimum energy level, a maximum performance value, a maximum accuracy value, and a minimum bitrate level.

4. The computer system according to claim 1, wherein the field programmable gate array is part of a pixel processor architecture.

5. The computer system according to claim 4, wherein the one or more hardware parameters of the pixel processor architecture that is used for generating the the collection of Pareto-optimal hardware realizations is selected from the group consisting of:

a number of cores, a number of bits of an input pixel, a number of bits of an output pixel, and a frequency of operation.

6. The computer system according to claim 4, wherein each pixel of the pixel processor architecture is processed independently of any other pixel.

7. The computer system according to claim 1, wherein the field programmable gate array is part of a digital filtering architecture.

8. The computer system according to claim 7, wherein the digital filtering architecture is one-dimensional.

9. The computer system according to claim 7, wherein the digital filtering architecture is two-dimensional.

10. The computer system according to claim 7, wherein the digital filtering architecture includes image or video compression accomplished using the Discrete Cosine Transform (DCT) hardware core that can be parameterized using a different number of bits for representing input, output, and DCT filter coefficients and a software coefficient that consists of a Quality Factor.

11. The computer system according to claim 7, wherein the one or more hardware parameters of the digital filtering architecture are selected from the group consisting of:

a number of coefficients, a number of bits representing the number of coefficients, and a number of bits representing the output.

12. A computer system including a processor, a memory, and a field programmable gate array for producing a dynamically reconfigurable framework for performing a task comprising the steps of:

varying by the processor one or more hardware parameters to generate a plurality of hardware realizations, each hardware realization associated with one or more of;

power measurements, performance measurements, bitrate measurements and accuracy measurements;

obtaining by the processor one or more objectives for each hardware realization to obtain hardware objectives, wherein the hardware objectives consist of a power value, an energy value, a performance value, a bitrate value, and an accuracy value;

using the hardware objectives by the processor to determine the hardware realizations of the plurality that are Pareto-optimal to obtain a collection of Pareto-optimal hardware realizations;

storing in memory the collection of Pareto-optimal hardware realizations and the hardware objectives;

selecting by the processor one or more Pareto-optimal hardware realizations from the plurality that meet or exceed one or more time-varying constraints or minimize the violation of the time-varying constraints; and

programming the field programmable gate array with the one or more Pareto-optimal hardware realizations, wherein the field programmable gate array is part of an image or video processing and communications system where processing is based on a digital filtering architecture and compression is based on a Discrete Cosine Transform (DCT) hardware core that is parameterized using a different number of bits for representing inputs, outputs, and DCT filter coefficients and a software coefficient that consists of a Quality Factor, the programming step further comprises the step of using by the processor one or more selected from the group comprising of;

a dynamic partial reconfiguration, one or more software parameters, and a dynamic frequency control.

13. The computer system according to claim 12, wherein the one or more hardware parameters include frequency of operation.

14. The computer system according to claim 12, wherein the one or more time-varying constraints are selected from the group consisting of:

a minimum power value, a minimum energy level, a maximum performance value, a maximum accuracy value, and a minimum bitrate level.

15. The computer system according to claim 12, wherein the digital filtering architecture comprises of a pixel processor architecture.

16. The computer system according to claim 15, wherein the one or more hardware parameters of the pixel processor architecture that is used for generating the the collection of Pareto-optimal hardware realizations is selected from the group consisting of:

a number of cores, a number of bits of an input pixel, a number of bits of an output pixel, and a frequency of operation.

17. The computer system according to claim 15, wherein each pixel of the pixel processor architecture is processed independently of any other pixel.

18. The computer system according to claim 12 wherein the digital filtering architecture is one-dimensional.

19. The computer system according to claim 12, wherein the digital filtering architecture is two-dimensional.

20. The computer system according to claim 12, wherein the one or more hardware parameters of the digital filtering architecture are selected from the group consisting of:

a number of coefficients, a number of bits representing the number of coefficients, and a number of bits representing the output.