Graphics accelerator

• US 9,111,369 B2
• Filed: 03/01/2013
• Issued: 08/18/2015
• Est. Priority Date: 11/09/1998
• Status: Expired due to Fees

• Current Assignee: Broadcom Corporation (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: MacInnis, Alexander G., Tang, Chengfuh Jeffrey, Xie, Xiadong, Patterson, James T., Kranawetter, Greg A.
• Primary Examiner(s): Richer, Joni
• Application Number:
  US13/782,081
• Publication Number:
  US 20140078155A1
• Time in Patent Office: 900 Days
• Field of Search: 345/501, 345/502, 345/505, 345/506, 345/519, 345/530, 345/531, 345536-538, 345/541
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 9/00 Image coding bandwidth or redundancy reduction for static pictures H04N1/41; coding or decoding of static colour picture signals H04N1/64; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/02 : characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/024 : using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/026 : Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/06 : using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 : Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 : Display of multiple viewports
• CPC Class Codes: G09G 5/28 : for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 : for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 : characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: G09G 5/363 : Graphics controllers
• CPC Class Codes: H04N 11/143 : Encoding means therefor H04N11/16 takes precedence
• CPC Class Codes: H04N 11/20 : Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 : characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 : using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 : Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/59 : involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 21/42204 : User interfaces specially adapted for controlling a client device through a remote control device; Remote control devices therefor constructive details of casings for the remote control device H01H9/0235; user interfaces for controlling a tuning device of a television receiver through a remote control H03J9/00; remote control of peripheral devices connected to a television receiver through the remote control device of the television receiver H04B1/205
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 : for processing graphics
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/440263 : by altering the spatial resolution, e.g. for displaying on a connected PDA
• CPC Class Codes: H04N 21/4438 : Window management, e.g. event handling following interaction with the user interface
• CPC Class Codes: H04N 21/47 : End-user applications
• CPC Class Codes: H04N 5/04 : Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 5/126 : whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/0122 : the input and the output signals having different aspect ratios
• CPC Class Codes: H04N 7/0135 : involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59
• CPC Class Codes: H04N 9/45 : Generation or recovery of colour sub-carriers
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 : Multi-standard receivers

Abstract

Disclosed herein are various embodiments of a graphics accelerator, which may include an integrated circuit. The integrated circuit may include a local memory; a direct memory access (DMA) engine; a processor; and one or more processing pipelines. The local memory stores graphics data that includes a plurality of pixels. The DMA engine transfers the graphics data between the local memory and an external memory. The processor performs at least one operation, in parallel, on components of at least a portion of the pixels. The one or more processing pipelines process the graphics data. The graphics accelerator works on operands and produces outputs for one set of pixels while the DMA engine is bringing in operands for a future set of pixel operations, and transfers data from the external memory to the one or more processing pipelines by directing data to the one or more pipelines.

Claims

1. A graphics accelerator comprising:

an integrated circuit comprising;

a local memory operable to store graphics data, the graphics data comprising a plurality of pixels;

a direct memory access (DMA) engine operable to transfer the graphics data between the local memory and an external memory that is external to the graphics accelerator;

a processor operable to perform at least one operation, in parallel, on a plurality of components of at least a portion of the plurality of pixels, the plurality of components of a single pixel contained within a vector and the at least one operation comprising at least one vector operation, the processor operable to perform the at least one vector operation on the vector to process the plurality of components of the single pixel in parallel;

one or more processing pipelines operable to process the graphics data; and

wherein the graphics accelerator is operable to, at least;

work on operands and produce outputs for one set of pixels, while the DMA engine is bringing in operands for a future set of pixel operations; and

transfer data from the external memory to the one or more processing pipelines by directing data to the one or more pipelines.

2. The graphics accelerator of claim 1, where the graphics accelerator is operable to transfer the data by directing the data from the external memory directly to the one or more processing pipelines.

3. The graphics accelerator of claim 1, where the graphics accelerator is operable to transfer the data by directing the data to respective first-in-first-out (FIFO) input buffers of the one or more processing pipelines.

4. The graphics accelerator of claim 1, where the graphics accelerator is operable to transfer the data by directing the data from the external memory to the one or more processing pipelines via the local memory.

5. The graphics accelerator of claim 1, wherein the one or more processing pipelines comprise a plurality of sequential graphics data processing components.

6. The graphics accelerator of claim 1, wherein the at least one operation is a single type of operation performed in parallel on the plurality of components of the single pixel.

7. The graphics accelerator of claim 1, wherein the at least one operation comprises a plurality of operations of different types, performed in parallel on the plurality of components of the single pixel.

8. The graphics accelerator of claim 1, wherein the plurality of components comprise a plurality of color components, and wherein the processor is operable to perform the at least one operation on the plurality of color components of the single pixel in parallel.

9. The graphics accelerator of claim 8, wherein the plurality of color components comprise at least one of:

an R component, a G component, and a B component of an RGB color space;

or

a Y component, a U component, and a V component of a YUV color space.

10. A graphics accelerator comprising:

an integrated circuit comprising;

a local memory operable to store graphics data, the graphics data comprising a plurality of pixels;

a processor operable to perform at least one operation, in parallel, on a plurality of components of at least a portion of the pixels, the plurality of components of a single pixel contained within a vector and the at least one operation comprising at least one vector operation, the processor operable to perform the at least one vector operation on the vector to process the plurality of components of the single pixel in parallel;

one or more processing pipelines operable to process the graphics data; and

a direct memory access (DMA) engine operable to transfer the graphics data between the local memory and an external memory that is external to the graphics accelerator,

wherein the graphics accelerator is operable to, at least;

operate on graphics data corresponding to a present set of pixels while the DMA engine transfers graphics data corresponding to a future set of pixels; and

transfer data between the external memory and the one or more processing pipelines by directing data between the external memory and the one or more pipelines.

11. The graphics accelerator of claim 10, where the graphics accelerator is operable to transfer the data by directing the data from the external memory directly to the one or more processing pipelines.

12. The graphics accelerator of claim 10, where the graphics accelerator is operable to transfer the data by directing the data to respective first-in-first-out (FIFO) input buffers of the one or more processing pipelines.

13. The graphics accelerator of claim 10, where the graphics accelerator is operable to transfer the data by directing the data from the external memory to the one or more processing pipelines via the local memory.

14. The graphics accelerator of claim 10, wherein the one or more processing pipelines comprise a plurality of sequential graphics data processing components.

15. The graphics accelerator of claim 10, wherein the at least one operation is a single type of operation performed in parallel on the plurality of components of the single pixel.

16. The graphics accelerator of claim 10, wherein the at least one operation comprises a plurality of operations of different types, performed in parallel on the plurality of components of the single pixel.

17. A graphics accelerator comprising:

an integrated circuit comprising;

a local memory operable to store graphics data, the graphics data representing a plurality of pixels;

a direct memory access (DMA) engine operable to transfer the graphics data between the local memory and an external memory that is external to the graphics accelerator;

a processor operable to perform at least one operation, in parallel, on a plurality of components of at least a portion of the pixels, the plurality of components of a single pixel contained within a vector and the at least one operation comprising at least one vector operation, the processor operable to perform the at least one vector operation on the vector to process the plurality of components of the single pixel in parallel;

one or more processing pipelines operable to process the graphics data;

first circuitry operable to operate on graphics data corresponding to a present set of pixels while the DMA engine transfers graphics data corresponding to a future set of pixels; and

second circuitry operable to transfer data from the external memory to the one or more processing pipelines by directing data to the one or more pipelines.

18. The graphics accelerator of claim 17, where the second circuitry is operable to transfer the data by directing the data from the external memory directly to the one or more processing pipelines.

19. The graphics accelerator of claim 17, where the second circuitry is operable to transfer the data by directing the data to respective first-in-first-out (FIFO) input buffers of the one or more processing pipelines.

20. The graphics accelerator of claim 17, where the second circuitry is operable to transfer the data by directing the data from the external memory to the one or more processing pipelines via the local memory.

21. The graphics accelerator of claim 17, wherein the at least one operation is a single type of operation performed in parallel on the plurality of components of the single pixel.

22. The graphics accelerator of claim 17, wherein the at least one operation comprises a plurality of operations of different types, performed in parallel on the plurality of components of the single pixel.