De-duplication in flash memory module

• US 9,111,618 B2
• Filed: 07/11/2014
• Issued: 08/18/2015
• Est. Priority Date: 10/26/2010
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kawamura, Atsushi, Ogawa, Junji
• Primary Examiner(s): Parikh, Kalpit
• Application Number:
  US14/329,171
• Publication Number:
  US 20140321208A1
• Time in Patent Office: 403 Days
• Field of Search: 711/103
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0641 De-duplication techniques
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series

Abstract

Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A flash memory module includes a plurality of flash memory chips and a memory controller. Each flash memory chip includes a plurality of blocks, each block including a plurality of physical pages, each physical page being a unit for writing/reading data. The memory controller is configured to manage a first set and a second set of user data and a guarantee code associated with the user data. If the first set and the second set of user data are the same, then the same data sets are stored in a first physical page and the first and second guarantee codes are stored in a second physical page.

Claims

1. A flash memory module, comprising:

a plurality of flash memory chips, each flash memory chip including a plurality of blocks, each block including a plurality of physical pages, wherein each physical page is a unit for writing/reading data; and

a memory controller configured to manage;

a first data set and a first guarantee code set, wherein;

the first data set includes a plurality of first user data,

the first guarantee code set includes a plurality of first guarantee codes, and

each of the plurality of first guarantee codes is associated with one of the plurality of first user data, and

a second data set and a second guarantee code set, wherein;

the second data set includes a plurality of second user data,

the second guarantee code set includes a plurality of second guarantee codes, and

each of the plurality of second guarantee codes is associated with one of the plurality of second user data, and

wherein if the first data set and the second data set are a same data set, the memory controller is further configured to;

store the same data set into a first physical page, and

store both the first guarantee code set and the second guarantee code set into a second physical page.

2. The flash memory module according to claim 1, wherein each of the plurality of first guarantee codes and each of the plurality of second guarantee codes includes:

a bit error correction code part calculated from the user data associated with the guarantee code; and

a target data address part, which is an address of the user data associated with the guarantee code.

3. The flash memory module according to claim 1, wherein each of the plurality of first guarantee codes and each of the plurality of second guarantee codes are different.

4. The flash memory module according to claim 1, wherein a location of each of the plurality of first guarantee codes and each of the plurality of second guarantee codes in the second physical page is stored as an offset value relative to a top address of the second physical page.

5. The flash memory module according to claim 4, wherein the offset value is stored in a logical/physical address conversion table.

6. The flash memory module according to claim 1, wherein the first physical page and the second physical page are located in different blocks.

7. The flash memory module according to claim 1, wherein the memory controller is further configured to perform read processing, including:

acquiring a logical page address to be read;

acquiring target logical/physical address information from a logical/physical address conversion table;

determining whether the acquired logical page was subject to de-duplication processing;

if the acquired logical page was not subject to de-duplication processing, then acquiring a physical page address corresponding to the logical page;

if the acquired logical page was subject to de-duplication processing, then;

acquiring a physical page data address where a data part of the logical page is stored;

acquiring a physical page code address where guarantee codes of the logical page are stored; and

acquiring a physical page code offset address to identify a physical location of the guarantee codes within the physical page; and

reading data stored in a physical page based on the physical page address.

8. The flash memory module according to claim 1, wherein if there is an unused area in a physical page storing the first guarantee code set or the second guarantee code set, the memory controller is further configured to:

merge the first guarantee code set and the second guarantee code set into a single physical page by copying the first guarantee code set and the second guarantee code set to a new physical page and releasing the physical pages where the first guarantee code set and the second guarantee code set were previously stored.

9. A storage apparatus, comprising:

a storage controller; and

a plurality of flash memory modules, each of the plurality of flash memory modules including;

a plurality of flash memory chips, each flash memory chip including a plurality of blocks, each block including a plurality of physical pages, wherein each physical page is a unit for writing/reading data; and

a memory controller configured to manage;

a first data set and a first guarantee code set, wherein;

the first data set includes a plurality of first user data,

the first guarantee code set includes a plurality of first guarantee codes, and

each of the plurality of first guarantee codes is associated with one of the plurality of first user data, and

a second data set and a second guarantee code set, wherein;

the second data set includes a plurality of second user data,

the second guarantee code set includes a plurality of second guarantee codes, and

each of the plurality of second guarantee codes is associated with one of the plurality of second user data, and

wherein if the first data set and the second data set are a same data set, the memory controller is further configured to;

store the same data set into a first physical page, and

store both the first guarantee code set and the second guarantee code set into a second physical page.

10. The storage apparatus according to claim 9, wherein each of the plurality of first guarantee codes and each of the plurality of second guarantee codes includes:

a bit error correction code part calculated from the user data associated with the guarantee code; and

a target data address part, which is an address of the user data associated with the guarantee code.

11. The storage apparatus according to claim 9, wherein each of the plurality of first guarantee codes and each of the plurality of second guarantee codes are different.

12. The storage apparatus according to claim 9, wherein a location of each of the plurality of first guarantee codes and each of the plurality of second guarantee codes in the second physical page is stored as an offset value relative to a top address of the second physical page.

13. The storage apparatus according to claim 12, wherein the offset value is stored in a logical/physical address conversion table.

14. The storage apparatus according to claim 9, wherein the first physical page and the second physical page are located in different blocks.

15. The storage apparatus according to claim 9, wherein the memory controller is further configured to perform read processing, including:

acquiring a logical page address to be read;

acquiring target logical/physical address information from a logical/physical address conversion table;

determining whether the acquired logical page was subject to de-duplication processing;

if the acquired logical page was not subject to de-duplication processing, then acquiring a physical page address corresponding to the logical page;

if the acquired logical page was subject to de-duplication processing, then;

acquiring a physical page data address where a data part of the logical page is stored;

acquiring a physical page code address where guarantee codes of the logical page are stored; and

acquiring a physical page code offset address to identify a physical location of the guarantee codes within the physical page; and

reading data stored in a physical page based on the physical page address.

16. The storage apparatus according to claim 9, wherein if there is an unused area in a physical page storing the first guarantee code set or the second guarantee code set, the memory controller is further configured to:

merge the first guarantee code set and the second guarantee code set into a single physical page by copying the first guarantee code set and the second guarantee code set to a new physical page and releasing the physical pages where the first guarantee code set and the second guarantee code set were previously stored.