Semiconductor component and method of manufacture

• US 9,111,758 B2
• Filed: 07/25/2014
• Issued: 08/18/2015
• Est. Priority Date: 08/09/2013
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Chen, Yupeng, Liu, Rong, Holland, Phillip, Sharma, Umesh, Wall, Ralph
• Primary Examiner(s): Rodela, Eduardo A
• Application Number:
  US14/341,377
• Publication Number:
  US 20150041953A1
• Time in Patent Office: 389 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/04 the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
• CPC Class Codes: H01L 21/06 the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
• CPC Class Codes: H01L 21/18 the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials H01L21/041 - H01L21/0425, H01L21/045 - H01L21/048 take precedence
• CPC Class Codes: H01L 21/20 Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0664 Vertical bipolar transistor in combination with diodes
• CPC Class Codes: H01L 27/0676 comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248
• CPC Class Codes: H05K 9/0067 Devices for protecting against damage from electrostatic discharge

Abstract

In accordance with an embodiment, a semiconductor component includes a common mode filter monolithically integrated with a protection device. The common mode filter may be composed of first, second, third, and fourth coils, wherein each coil has first and second terminals and the first coil is magnetically coupled to the second coil and the third coil is magnetically coupled to the fourth coil. The protection device has a first terminal coupled to the first terminal of the first coil and a second terminal coupled to the first terminal of the third coil. An energy storage element has a terminal coupled to the second and first terminals of the first and second coils, respectively. Another embodiment includes monolithically integrating a common mode filter with a protection device and monolithically integrating a metal-insulator-metal capacitor with the common mode filter.

Claims

1. A method for manufacturing a semiconductor component having a common mode filter monolithically integrated with a protection device, comprising:

providing a semiconductor material having a major surface and a resistivity of at least 10 ohm-centimeters;

forming a plurality of trenches in the semiconductor material;

forming the protection device from the semiconductor material between first and second trenches of the plurality of trenches;

monolithically integrating a common mode filter with the protection device; and

monolithically integrating a metal-insulator-metal capacitor with the common mode filter.

2. The method of claim 1, wherein providing the semiconductor material comprises:

providing a semiconductor substrate having a resistivity of at least 5 ohm-centimeters;

forming a first epitaxial layer of a first conductivity type over the semiconductor substrate; and

forming a second epitaxial layer of a second conductivity type over the first epitaxial layer.

3. The method of claim 2, further including forming a buried layer of the first conductivity type from portions of the first and second epitaxial layers.

4. The method of claim 3, wherein forming the plurality of trenches includes forming at least first, second, third, and fourth trenches, wherein a portion of the semiconductor material between the first and second trenches serves as a first device region, a portion of the semiconductor material between the second and third trenches serves as a second device region, and a portion of the semiconductor material between the third and fourth trenches serves as a third device region.

5. The method of claim 4, further including forming a first diode from the first device region, a second diode from the second device region, and a transistor from the third device region.

6. The method of claim 4, further including:

forming a first and second dopant regions of the second conductivity type in the third device region;

forming third and fourth dopant regions of the second conductivity type in the first and second dopant regions and fifth and sixth dopant regions of the second conductivity type in the first and second device regions, respectively; and

forming seventh and eighth dopant regions of the first conductivity type in the first and second device regions, respectively.

7. The method of claim 4, further including:

forming a first dielectric layer over the semiconductor material, the first dielectric layer configured to magnetically decouple the common mode filter from the protection structure;

forming a first coil of the common mode filter over the first dielectric layer;

forming a second dielectric layer over the first coil and the first dielectric layer; and

forming a second coil over the second dielectric layer, the second dielectric layer configured to magnetically coupled the first coil and the second coil.

8. The method of claim 7, further including forming a third layer of dielectric material over the second coil and the second layer of dielectric material.

9. The method of claim 8, wherein the first, second, and third layers of dielectric material are photosensitive polyimides.

10. The method of claim 4, wherein monolithically integrating the metal-insulator-metal capacitor comprises:

forming a first layer of dielectric material over the semiconductor material;

forming a first layer of electrically conductive material over the first layer of dielectric material;

forming a second layer of dielectric material over first layer of electrically conductive material; and

forming a second layer of electrically conductive material over the second layer of dielectric material.

11. A method for manufacturing a semiconductor component having a common mode filter monolithically integrated with a protection device, comprising:

providing a semiconductor material having a major surface and a resistivity of at least 10 ohm-centimeters;

forming a plurality of trenches in the semiconductor material;

forming the protection device from the semiconductor material between first and second trenches of the plurality of trenches;

monolithically integrating a common mode filter with the protection device, the common mode filter comprising;

a first coil having first and second terminals;

a second coil having first and second terminals, the first terminal of the second coil coupled to the second terminal of the first coil, the first coil magnetically coupled to the second coil;

a third coil having first and second terminals;

a fourth coil having first and second terminals, the first terminal of the fourth coil coupled to the second terminal of the third coil, the third coil magnetically coupled to the fourth coil; and

monolithically integrating a metal-insulator-metal capacitor with the common mode filter.

12. The method of claim 11, wherein providing the semiconductor material comprises:

providing a semiconductor substrate having a resistivity of at least 5 ohm-centimeters;

forming a first epitaxial layer of a first conductivity type over the semiconductor substrate; and

forming a second epitaxial layer of a second conductivity type over the first epitaxial layer.

13. The method of claim 12, further including forming a buried layer of the first conductivity type from portions of the first and second epitaxial layers.

14. The method of claim 13, wherein forming the plurality of trenches includes forming at least first, second, third, and fourth trenches, wherein a portion of the semiconductor material between the first and second trenches serves as a first device region, a portion of the semiconductor material between the second and third trenches serves as a second device region, and a portion of the semiconductor material between the third and fourth trenches serves as a third device region.

15. The method of claim 14, further including forming a first diode from the first device region, a second diode from the second device region, and a transistor from the third device region.

16. The method of claim 14, further including:

forming a first and second dopant regions of the second conductivity type in the third device region;

forming third and fourth dopant regions of the second conductivity type in the first and second dopant regions and fifth and sixth dopant regions of the second conductivity type in the first and second device regions, respectively; and

forming seventh and eighth dopant regions of the first conductivity type in the first and second device regions, respectively.

17. The method of claim 14, further including:

forming a first dielectric layer over the semiconductor material, the first dielectric layer configured to magnetically decouple the common mode filter from the protection structure;

forming a first coil of the common mode filter over the first dielectric layer;

forming a second dielectric layer over the first coil and the first dielectric layer; and

forming a second coil over the second dielectric layer, the second dielectric layer configured to magnetically coupled the first coil and the second coil.

18. The method of claim 17, further including forming a third layer of dielectric material over the second coil and the second layer of dielectric material.

19. The method of claim 18, wherein the first, second, and third layers of dielectric material are photosensitive polyimides.

20. The method of claim 14, wherein monolithically integrating the metal-insulator-metal capacitor comprises:

forming a first layer of dielectric material over the semiconductor material;

forming a first layer of electrically conductive material over the first layer of dielectric material;

forming a second layer of dielectric material over first layer of electrically conductive material; and

forming a second layer of electrically conductive material over the second layer of dielectric material.