Semiconductor structure with improved channel stack and method for fabrication thereof

• US 9,111,785 B2
• Filed: 07/31/2013
• Issued: 08/18/2015
• Est. Priority Date: 03/03/2011
• Status: Expired due to Fees

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Gregory, Paul E., Ranade, Pushkar, Shifren, Lucian
• Primary Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US13/955,787
• Publication Number:
  US 20130313652A1
• Time in Patent Office: 748 Days
• Field of Search: 257368-369, 257/77, 257/351, 257/328, 257/288, 257/E21.4, 257/E21.33, 257/E21.54, 438/199
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method for fabricating a semiconductor structure with a channel stack includes forming a screening layer under a gate of a PMOS transistor element and a NMOS transistor element, forming a threshold voltage control layer on the screening layer, and forming an epitaxial channel layer on the threshold control layer. At least a portion of the epitaxial channel layers for the PMOS transistor element and the NMOS transistor element are formed as a common blanket layer. The screening layer for the PMOS transistor element may include antimony as a dopant material that may be inserted into the structure prior to or after formation of the epitaxial channel layer.

Claims

1. A transistor structure with a channel stack, the transistor structure having a semiconductor substrate with a plurality of pre-formed doped wells formed therein, comprising:

a first region having;

a first doped well providing a foundation for a PMOS transistor element;

a first doped screening layer implanted in the semiconductor substrate in contact with the first doped well;

a first doped threshold voltage control layer in contact with the first doped screening layer;

a second region having;

a second doped well providing a foundation for an NMOS transistor element;

a second doped screening layer implanted in the semiconductor substrate in contact with the second well;

a second doped threshold voltage control layer in contact with the second doped screening layer; and

a third layer formed from undoped epitaxial blanket deposition on the semiconductor substrate, separate from and on top of the first and second doped threshold voltage control layers, the third undoped epitaxial layer allowing establishment of an intrinsic channel for each of the PMOS and NMOS transistor elements;

a fourth layer formed from undoped epitaxial blanket deposition on the third layer for only one of the PMOS and NMOS transistor elements so that one of the PMOS and NMOS transistor elements has an overall undoped epitaxial intrinsic channel layer thickness greater than the other one of the PMOS and NMOS transistor elements.

2. The transistor structure of claim 1, wherein the first doped threshold voltage control layer comprises dopants selected from the group consisting of antimony and arsenic.

3. The transistor structure of claim 1, wherein the first doped screening layer is doped with antimony or arsenic.

4. The transistor structure of claim 1, further comprising:

a body tap coupled to at least one of the first doped well and the second doped well.

5. A transistor structure with a channel stack, the transistor structure having a semiconductor substrate with a plurality of pre-formed doped wells formed therein, comprising:

a first region having;

a first doped well providing a foundation for a first PMOS transistor element;

a first doped screening layer implanted in the semiconductor substrate in contact with the first doped well;

a first doped threshold voltage control layer in contact with the first doped screening layer;

a second region having;

a second doped well providing a foundation for a first NMOS transistor element;

a second doped screening layer implanted in the semiconductor substrate in contact with the second well;

a second doped threshold voltage control layer in contact with the second doped screening layer; and

a third layer formed from undoped epitaxial blanket deposition on the semiconductor substrate, separate from and on top of the first and second doped threshold voltage control layers, the third undoped epitaxial layer allowing establishment of an intrinsic channel for each of the first PMOS and first NMOS transistor elements;

one or more additional PMOS transistor elements formed in the semiconductor substrate in a same manner as the first PMOS transistor element;

a fourth layer formed from undoped epitaxial blanket deposition on the third layer when deposited only on the one or more additional PMOS transistor elements so that an overall undoped epitaxial intrinsic channel layer thickness for the one or more additional PMOS transistor elements is greater than that of the first PMOS transistor element.

6. The transistor structure of claim 5, wherein the first doped threshold voltage control layer comprises dopants selected from the group consisting of antimony and arsenic.

7. The transistor structure of claim 5, wherein the first doped screening layer is doped with antimony or arsenic.

8. The transistor structure of claim 5, further comprising:

a body tap coupled to at least one of the first doped well and the second doped well.

9. A transistor structure with a channel stack, the transistor structure having a semiconductor substrate with a plurality of pre-formed doped wells formed therein, comprising:

a first region having;

a first doped well providing a foundation for a first PMOS transistor element;

a first doped screening layer implanted in the semiconductor substrate in contact with the first doped well;

a first doped threshold voltage control layer in contact with the first doped screening layer;

a second region having;

a second doped well providing a foundation for a first NMOS transistor element;

a second doped screening layer implanted in the semiconductor substrate in contact with the second well;

a second doped threshold voltage control layer in contact with the second doped screening layer; and

a third layer formed from undoped epitaxial blanket deposition on the semiconductor substrate, separate from and on top of the first and second doped threshold voltage control layers, the third undoped epitaxial layer allowing establishment of an intrinsic channel for each of the first PMOS and first NMOS transistor elements;

one or more additional NMOS transistor elements formed in the semiconductor substrate in a same manner as the first NMOS transistor element; and

a fourth layer formed from undoped epitaxial blanket deposition on the third layer when deposited only on the one or more additional NMOS transistor elements so that an overall undoped epitaxial intrinsic channel layer thickness for the one or more additional NMOS transistor elements is greater than that of the first NMOS transistor element.

10. The transistor structure of claim 9, wherein the first doped threshold voltage control layer comprises dopants selected from the group consisting of antimony and arsenic.

11. The transistor structure of claim 9, wherein the first doped screening layer is doped with antimony or arsenic.

12. The transistor structure of claim 9, further comprising:

a body tap coupled to at least one of the first doped well and the second doped well.