Thin film transistor array panel

• US 9,111,789 B2
• Filed: 03/13/2014
• Issued: 08/18/2015
• Est. Priority Date: 06/10/2013
• Status: Active Grant

• Current Assignee: Industry-University Cooperation Foundation Hanyang University, Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Industry-University Cooperation Foundation Hanyang University, Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Jeon, Hyeong Tag, Lee, Jae Sang, Cho, Byung Su
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US14/209,066
• Publication Number:
  US 20140361304A1
• Time in Patent Office: 523 Days
• Field of Search: 257/66, 257/368
• US Class Current: 1/1
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor array panel includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate and overlapping the gate electrode; a plurality of nano particles disposed on or in the semiconductor layer; a source electrode disposed on the substrate; and a drain electrode disposed on the substrate, where the source electrode and the drain electrode are spaced apart from each other, and the semiconductor layer is disposed between the source electrode and the drain electrode, in which a diameter of each of the nano particles is in a range of about 2 nm to about 5 nm, or a ratio of a plane area of the nano particles per unit area of the semiconductor layer is in a range of about 5% to about 80%.

Claims

1. A thin film transistor array panel, comprising:

a substrate;

a gate electrode disposed on the substrate;

a semiconductor layer disposed on the substrate and overlapping the gate electrode;

a plurality of nano particles disposed on or in the semiconductor layer;

a source electrode disposed on the substrate; and

a drain electrode disposed on the substrate, wherein the source electrode and the drain electrode are spaced apart from each other, and the semiconductor layer is disposed between the source electrode and the drain electrode,

wherein a diameter of each of the nano particles is about 2 nanometers to about 5 nanometers, and

wherein the nano particles are disposed on a first surface of the semiconductor layer, where a second surface of the semiconductor layer, which is opposite to the first surface, faces the gate electrode.

2. The thin film transistor array panel of claim 1, wherein

the nano particles comprise a metal.

3. The thin film transistor array panel of claim 2, wherein

the nano particles comprise gold (Au), silver (Ag), platinum (Pt), copper (Cu), aluminum (Al), tin (Sn), indium (In), a transition metal, a metal oxide thereof, or a combination thereof,

wherein the transition metal comprises titanium (Ti), nickel (Ni), cobalt (Co), chromium (Cr), ruthenium (Ru), molybdenum (Mo), zinc (Zn), zirconium (Zr), tungsten (W), or a combination thereof.

4. The thin film transistor array panel of claim 2, wherein

the nano particles comprise:

a first layer comprising the metal; and

a second layer surrounding the first layer and comprising a metal oxide of the metal.

5. The thin film transistor array panel of claim 1, wherein

the nano particles have a spherical shape, a disk type, a rod type, or a plate shape.

6. A thin film transistor array panel comprising:

a substrate;

a gate electrode disposed on the substrate;

a semiconductor layer disposed on the substrate and overlapping the gate electrode;

a plurality of nano particles disposed on or in the semiconductor layer; and

a source electrode disposed on the substrate; and

a drain electrode disposed on the substrate, wherein the source electrode and the drain electrode are spaced apart from each other, and the semiconductor layer is between the source electrode and the drain electrode,

wherein a ratio of a plane area of the nano particles per unit area of the semiconductor layer is in a range of about 5% to about 80%, and

wherein the nano particles are disposed on a first surface of the semiconductor layer, where a second surface of the semiconductor layer, which is opposite to the first surface, faces the gate electrode.

7. The thin film transistor array panel of claim 6, wherein

the nano particles include a metal.

8. The thin film transistor array panel of claim 7, wherein

the nano particles comprise gold (Au), silver (Ag), platinum (Pt), copper (Cu), aluminum (Al), tin (Sn), and indium (In), a transition metal, a metal oxide thereof, or a combination thereof,

wherein the transition metal comprises titanium (Ti), nickel (Ni), cobalt (Co), chromium (Cr), ruthenium (Ru), molybdenum (Mo), zinc (Zn), zirconium (Zr), tungsten (W), or a combination thereof.

9. The thin film transistor array panel of claim 7, wherein

the nano particles comprise:

a first layer including the metal; and

a second layer surrounding the first layer and comprising a metal oxide of the metal.

10. The thin film transistor array panel of claim 6, wherein

the nano particles have a spherical shape, a disk type, a rod type, or a plate shape.