Thin film transistor panel having an etch stopper on semiconductor

• US 9,111,805 B2
• Filed: 03/31/2014
• Issued: 08/18/2015
• Est. Priority Date: 02/11/2010
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Yun, Pil-Sang, Kim, Ki-Won, Ryu, Hye-Young, Lee, Woo-Geun, Choi, Seung-Ha, Youn, Jae-Hyoung, Chung, Kyoung-Jae, Lee, Young-Wook, Lee, Je-Hun, Yoon, Kap-Soo, Kim, Do-Hyun, Yang, Dong-Ju, Choi, Young-Joo
• Primary Examiner(s): Pham, Hoai V
• Application Number:
  US14/230,787
• Publication Number:
  US 20140209903A1
• Time in Patent Office: 505 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/465 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/469
• CPC Class Codes: H01L 21/475 using masks
• CPC Class Codes: H01L 21/47573 Etching the layer
• CPC Class Codes: H01L 21/47635 After-treatment of these layers
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Claims

1. A panel comprising a thin film transistor, the panel comprising:

a substrate;

a first electrode on the substrate;

a first insulating layer on the first electrode;

an oxide semiconductor pattern on the first insulating layer;

an etch stopper on the oxide semiconductor pattern;

a second electrode and a third electrode on the etch stopper and the oxide semiconductor pattern,

wherein the first insulating layer comprises a first region disposed under the etch stopper and a second region disposed outside the first region, and

wherein a thickness of the first region exceeds a thickness of the second region.

2. The panel of claim 1, wherein an upper surface of the first region of the first insulating layer is a non-etched surface, and an upper surface of the second region of the first insulating layer is an etched surface.

3. The panel of claim 2, wherein at least one of the second electrode and the third electrode is disposed directly on the upper surface of the second region of the first insulating layer without being disposed directly on the upper surface of the first region of the first insulating layer.

4. The panel of claim 3, wherein the at least one of the second electrode and the third electrode is further disposed directly on a sidewall and an upper surface of the etch stopper.

5. The panel of claim 4, further comprising:

a second insulating layer on the second electrode and the third electrode and comprising a contact hole exposing the second electrode;

a fourth electrode on the second insulating layer and connected to the second electrode via the contact hole in the second insulating layer.

6. The panel of claim 5, wherein the second insulating layer comprises a passivation layer.

7. The panel of claim 5, wherein the second insulating layer comprises a color filter.

8. The panel of claim 5, wherein:

the oxide semiconductor pattern comprises one or more compounds represented by the formulas A_xB_xO_x and A_xB_xC_xO_x;

A is In, Zn, Ga, Hf, or Cd;

B is Zn, Ga, Sn, or In;

C is Sn, Zn, Cd, Ga, In, or Hf;

O is atomic oxygen;

each x is independently a non-zero integer; and

A, B, and C are different from one another.

9. The panel of claim 8, wherein the oxide semiconductor pattern comprises one or more of InZnO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, GaZnSnO, GaInZnO, or HfInZnO.

10. The panel of claim 1, wherein at least one of the second electrode and the third electrode is disposed directly on a sidewall and an upper surface of the oxide semiconductor pattern.

11. The panel of claim 1, wherein a pattern of the etch stopper is contained entirely within a perimeter of the oxide semiconductor pattern.