Array substrate, manufacturing method thereof and LCD

• US 9,111,814 B2
• Filed: 12/07/2011
• Issued: 08/18/2015
• Est. Priority Date: 12/22/2010
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Liu, Xiang, Xue, Jianshe
• Primary Examiner(s): Kim, Richard
• Assistant Examiner(s): Hsu, Kendrick
• Application Number:
  US13/313,132
• Publication Number:
  US 20120162585A1
• Time in Patent Office: 1,350 Days
• Field of Search: 349 42- 45, 438584-688, 438942-952
• US Class Current: 1/1
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: G02F 1/13625 Patterning using multi-mask exposure
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

There is disclosed an array substrate which has a base substrate and data lines and gate lines on the base substrate, The data lines and gate lines intersect with each other to define pixel units, and each pixel unit comprises a pixel electrode, a gate electrode, a source electrode, a drain electrode and an active layer, and the pixel electrode, the gate electrode and the gate line adjoin to the base substrate, and the gate electrode is formed of a same material as that for forming the pixel electrode.

Claims

1. A method for manufacturing an array substrate, comprising a step to form conductive layer patterns and insulation layer patterns on a base substrate,

wherein the conductive layer patterns at least comprise a gate line, a gate electrode, an active layer, a source electrode, a drain electrode, a data line and a pixel electrode, wherein the gate line does not overlap with the gate electrode;

and

wherein forming of the gate line, the gate electrode, and the pixel electrode comprises;

sequentially forming a transparent conductive thin film and a gate metal thin film on the base substrate;

applying photoresist on the gate metal thin film;

exposing with a double-tone mask plate and developing the photoresist to form a photoresist pattern comprising a photoresist-retained region, a photoresist-partially-retained region and a photoresist-removed region, wherein a photoresist thickness of the photoresist-retained region is larger than that in the photoresist-partially-retained region, the photoresist of the photoresist-retained region merely covers a region for forming the gate line, the photoresist of the photoresist-partially-retained region covers a region for forming the gate electrode and the pixel electrode, and the photoresist-removed region is other regions;

conducting a first etching to remove the gate metal thin film and the transparent conductive thin film in the photoresist-removed region to form the gate line;

ashing to remove the photoresist by the photoresist thickness in the photoresist-partially-retained region;

conducting a second etching to remove the gate metal thin film exposed in the photoresist-partially-retained region to form the gate electrode and the pixel electrode; and

removing the remaining photoresist.

2. The method according to claim 1, wherein the step to form the active layer, the source electrode, the drain electrode, the data line and the insulation layer patterns comprises:

forming a gate insulating layer and an active layer film on the base substrate formed with the gate line, the gate electrode, and the pixel electrode;

with a second double-tone mask plate, patterning the active layer film and the gate insulating layer to form a contact via hole and further patterning the active layer film to form the active layer;

forming a data line metal film on the base substrate formed with the active layer and the contact via hole;

with a first single-tone mask plate, patterning the data line metal film to form the data line, the source electrode and the drain electrode and further patterning the active layer to form a channel region, wherein the drain electrode is connected with the pixel electrode through the contact via hole;

forming a passivation layer on the base substrate formed with the data line, the source electrode and the drain electrode; and

with a second single-tone mask plate, patterning the passivation layer to form an interface region via hole.

3. The method according to claim 2, wherein the step of patterning the active layer film and the gate insulating layer to form a contact via hole and further patterning the active layer film to form the active layer with the second double-tone mask plate comprises:

applying photoresist on the active layer;

exposing with the second double-tone mask plate and developing the photoresist to form a photoresist pattern comprising a photoresist-retained region, a photoresist-partially-retained region and a photoresist-removed region, wherein a photoresist thickness of the photoresist-retained region is larger than that in the photoresist-partially-retained region;

conducting a first etching to pattern the active layer film and the gate insulating layer in the photoresist-removed region to form the contact via hole;

ashing to remove the photoresist by the photoresist thickness in the photoresist-partially-retained region;

conducting a second etching to pattern the active layer film exposed in the photoresist-partially-retained region to form the active layer; and

removing the remaining photoresist.

4. The method according to claim 2, wherein forming the active layer film on the base substrate formed with the gate line, the gate electrode, and the pixel electrode comprises:

forming a semiconductor layer of a thickness of 1000˜

3000 Å and

a heavily doped semiconductor layer of a thickness of 500˜

1000 Å

on the base substrate;

or

forming a metal oxide layer of a thickness of 100˜

1500 Å

as a semiconductor layer on the base substrate.

5. The method according to claim 1, wherein the step of sequentially forming the transparent conductive thin film and the gate metal thin film on the base substrate comprises:

depositing the transparent conductive thin film of a thickness of 300˜

600 Å and

the gate metal thin film of a thickness of 1000˜

4000 Å

on the base substrate.