Multilayer pillar for reduced stress interconnect and method of making same

• US 9,111,816 B2
• Filed: 03/27/2012
• Issued: 08/18/2015
• Est. Priority Date: 10/11/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Jadhav, Virendra R., Semkow, Krystyna W., Srivastava, Kamalesh K., Sundlof, Brian R.
• Primary Examiner(s): Kraig, William F
• Assistant Examiner(s): Doan, Nga
• Application Number:
  US13/431,609
• Publication Number:
  US 20120181071A1
• Time in Patent Office: 1,239 Days
• Field of Search: 257/737, 257/E21.506, 174/257, 438/121
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/1145 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13005 Structure
• CPC Class Codes: H01L 2224/13013 being rectangular or square
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13171 : Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/13184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/13599 : Material
• CPC Class Codes: H01L 2224/13655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13666 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13671 : Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/13684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/16235 : the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/29099 : Material
• CPC Class Codes: H01L 2224/29599 : Material
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/2064 : larger or equal to 1 micron less than 100 microns
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/35121 : Peeling or delaminating
• CPC Class Codes: H01L 2924/37001 : Yield
• CPC Class Codes: H01L 2924/384 : Bump effects
• CPC Class Codes: Y10T 156/10 : Methods of surface bonding and/or assembly therefor

Abstract

A multi-layer pillar is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

Claims

1. A structure comprising a modulated copper pillar including:

an uppermost layer that connects the modulated copper pillar to a chip and that prevents diffusion of materials between the chip and materials of the modulated copper pillar;

an upper copper layer;

at least one low strength, high ductility deformation region; and

a lower copper layer,

wherein the at least one low strength, high ductility deformation region is configured to absorb force imposed during chip assembly and thermal excursions,

wherein the at least one low strength, high ductility deformation region comprises at least two separate, low strength, high ductility deformation layers of the modulated copper pillar.

2. The structure of claim 1, wherein the at least one low strength, high ductility deformation region includes one of Tin, Bismuth and Indium.

3. The structure of claim 2, wherein a thickness of the at least one low strength, high ductility deformation region is about 0.5 to 20 microns in thickness.

4. The structure of claim 3, wherein the thickness is about 0.5 to 10 microns.

5. The structure of claim 1, wherein the at least one low strength, high ductility deformation region has a modulus of elasticity less than copper.

6. The structure of claim 1, wherein the at least one low strength, high ductility deformation region includes one of gold, aluminum and silver.

7. The structure of claim 6, wherein the at least one low strength, high ductility deformation region is about 0.2 to 1 microns in thickness.

8. The structure of claim 1, wherein:

the uppermost layer is comprised of a barrier and adhesion layer which is formed on, and entirely covers an upper surface of the upper copper layer;

the upper copper layer is formed on, and entirely covers an uppermost surface of the at least one low strength, high ductility deformation region;

a lowermost surface of the at least one low strength, high ductility deformation region is formed on, and entirely covers an uppermost surface of the lower copper layer; and

a lowermost surface of the lower copper layer is formed on, and entirely covers an uppermost surface of a solder disc.

9. The structure of claim 8, further comprising:

a first protective layer interposed at an interface between the uppermost surface of the at least one low strength, high ductility deformation region and the upper copper layer; and

a second protective layer interposed at an interface between the lowermost surface of the at least one low strength, high ductility deformation region and the lower copper layer.

10. The structure of claim 9, wherein:

the first protective layer is a layer of nickel covering the entire uppermost surface of the at least one low strength, high ductility deformation region; and

the second protective layer is another layer of nickel covering the entire lowermost most surface of the at least one low strength, high ductility deformation region.

11. The structure of claim 1, wherein the at least one low strength, high ductility deformation region is configured to slide or tilt during a heating cycle of the chip assembly.

12. An interconnect pillar comprising an intermediate layer interposed between an upper copper and a lower copper layer, wherein:

the intermediate layer having a lower modulus of elasticity than that of the upper copper and the lower copper layer;

the intermediate layer is structured to absorb stress imposed during a cooling cycle of an interconnect process with a chip which would otherwise be imparted to the chip; and

the intermediate layer is configured to slide or tilt during a heating cycle of the interconnect process with the chip, and

further comprising a second intermediate layer between the lower copper layer and another copper layer.

13. The interconnect pillar of claim 12, wherein the intermediate layer is one of Aluminum, Gold and Silver.

14. The interconnect pillar of claim 12, wherein the intermediate layer is one of Indium, Tin and Bismuth.

15. The interconnect pillar of claim 12, further comprising a cap layer formed beneath the lower copper layer, the cap layer having properties to bond the interconnect pillar to a substrate.

16. An interconnect pillar comprising:

a first copper layer;

a first nickel barrier protective layer;

a first intermediate layer;

a second nickel barrier protective layer; and

a second copper layer,

wherein;

the first copper layer, the first nickel barrier protective layer, the first intermediate layer, the second nickel barrier protective layer, and the second copper layer each have a substantially planar upper surface and a substantially planar lower surface,

the upper surface of first nickel barrier protective layer in direct contact with the lower surface of the first copper layer;

the upper surface of the first intermediate layer is in direct contact with the lower surface of the first nickel barrier protective layer;

the first intermediate layer has a modulus of elasticity lower than the first copper layer;

the upper surface of the second nickel barrier protective layer is in direct contact with the lower surface of the first planar intermediate layer;

the upper surface of the second copper layer is in direct contact with the lower surface of the second nickel barrier protective layer; and

the first intermediate layer having a modulus of elasticity lower than the second copper layer.

17. The interconnect pillar of claim 16, further comprising:

a second intermediate layer;

a third nickel barrier protective layer;

a fourth nickel barrier protective layer; and

a third copper layer,

wherein;

the second intermediate layer, the third nickel barrier protective layer, the fourth nickel barrier protective layer, and the third copper layer each have a substantially planar upper surface and a substantially planer lower surface;

the lower surface of the second copper layer is in direct contact with the upper surface of the third nickel barrier protective layer;

the lower surface of the third nickel barrier protective layer is in direct contact with the upper surface of the second intermediate layer;

the lower surface of the second intermediate layer is in direct contact with the upper surface of the fourth nickel barrier protective layer;

the lower surface of the fourth nickel barrier protective layer is in direct contact with the upper surface of the third copper layer; and

each of the first intermediate layer and second intermediate layer has a modulus of elasticity lower than each of the first, second, and third copper layers.

18. The interconnect pillar of claim 16, wherein the a first intermediate layer is configured to slide or tilt during a heating cycle of an interconnect process with a chip.