Method of forming split-gate cell for non-volative memory devices

• US 9,111,866 B2
• Filed: 03/07/2013
• Issued: 08/18/2015
• Est. Priority Date: 03/07/2013
• Status: Expired due to Fees

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Chen, Yu, Liu, Huajun, Chwa, Siow Lee, Siah, Soh Yun, Shao, Yanxia, Lim, Yoke Leng
• Primary Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US13/788,174
• Publication Number:
  US 20140252445A1
• Time in Patent Office: 894 Days
• Field of Search: 257/316, 257/325, 257/314, 257/324, 438/261, 438/201, 438/301, 438/593, 438/258, 438/591
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3213 Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

Fabrication of a slim split gate cell and the resulting device are disclosed. Embodiments include forming a first gate on a substrate, the first gate having an upper surface and a hard-mask covering the upper surface, forming an interpoly isolation layer on side surfaces of the first gate and the hard-mask, forming a second gate on one side of the first gate, with an uppermost point of the second gate below the upper surface of the first gate, removing the hard-mask, forming spacers on exposed vertical surfaces, and forming a salicide on exposed surfaces of the first and second gates.

Claims

1. A method comprising:

forming a first gate on a substrate, the first gate having an upper surface and a nitride hard-mask covering, and directly contacting, the upper surface;

forming an interpoly oxide layer or charge storage layer on side surfaces of the first gate and the nitride hard-mask;

depositing a blanket polysilicon layer;

etching the blanket polysilicon layer to form a polysilicon spacer with an uppermost point of the polysilicon spacer below the upper surface of the first gate on each side of the first gate;

removing the polysilicon spacer from a first side of the first gate, the remaining polysilicon spacer forming a second gate on a second side of the first gate opposite to the first side;

removing the nitride hard-mask;

forming spacers on all exposed vertical surfaces; and

forming a salicide on exposed surfaces of the first and second gates,

wherein the first gate is one of a select gate and a control gate, and the second gate is the other of a select gate and a control gate,

wherein an uppermost point of the interpoly oxide layer or charge storage layer on the first side is lower than an uppermost point of the second side and an uppermost point of the first gate is lower than the uppermost point of the interpoly oxide layer or charge storage layer on the first side.

2. The method according to claim 1, comprising forming the hard-mask of a nitride.

3. The method according to claim 1, comprising forming the interpoly oxide layer or charge storage layer of an oxide.

4. The method according to claim 1, comprising forming the interpoly oxide layer or charge storage layer on the substrate concurrently with forming the interpoly oxide layer or charge storage layer on side surfaces of the first gate.

5. The method according to claim 1, further comprising forming the interpoly oxide layer or charge storage layer between the first and second gates.