Three-dimensional semiconductor architecture
First Claim
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1. A semiconductor device comprising:
- a substrate with a first side and a second side, the substrate comprising an interior region and a periphery region surrounding the interior region;
first active devices on the first side of the substrate, at least one of the first active devices being located at least partially within the substrate;
a first set of through substrate vias located within the periphery region and extending from the first side of the substrate to the second side of the substrate; and
a second set of through substrate vias located within the interior region and extending from the first side of the substrate to the second side of the substrate, wherein the second set of through substrate vias are part of a power matrix, the second set of through substrate vias bisecting the substrate into a first part and a second part.
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Abstract
A system and method for making semiconductor die connections with through-substrate vias are disclosed. Through substrate vias are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment the substrate has an interior region and a periphery region surrounding the interior region. A first set of through substrate vias are located within the periphery region, and a second set of through substrate vias are located within the interior region, wherein the second set of through substrate vias are part of a power matrix. The second set of through substrate vias bisect the substrate into a first part and a second part.
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Citations
20 Claims
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1. A semiconductor device comprising:
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a substrate with a first side and a second side, the substrate comprising an interior region and a periphery region surrounding the interior region; first active devices on the first side of the substrate, at least one of the first active devices being located at least partially within the substrate; a first set of through substrate vias located within the periphery region and extending from the first side of the substrate to the second side of the substrate; and a second set of through substrate vias located within the interior region and extending from the first side of the substrate to the second side of the substrate, wherein the second set of through substrate vias are part of a power matrix, the second set of through substrate vias bisecting the substrate into a first part and a second part. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor device comprising:
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a substrate comprising a first side and a second side, with a first plurality of through vias around a periphery of the substrate and extending from the first side of the substrate to the second side of the substrate; active devices located at least partially within the first side of the substrate; and a set of power matrix through vias located within an interior of the substrate and extending from the first side of the substrate to the second side of the substrate, the interior being surrounded by the periphery, wherein the set of power matrix through vias are arranged in at least one straight line. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A semiconductor device comprising:
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a first semiconductor die and a second semiconductor die over the first semiconductor die; a first via last through via extending through the first semiconductor die; a second via last through via extending through the second semiconductor die, the second via last through via in electrical connection with the first via last through via; a first set of through vias extending through a periphery region of a substrate of the first semiconductor die, the first semiconductor die further comprising a first active device on a first side of the substrate; and a second set of through vias extending through an interior region of the substrate, the second set of through vias being a portion of a power matrix, and wherein the second set of through vias are in physical contact with a metallization layer adjacent to the first active device. - View Dependent Claims (17, 18, 19, 20)
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Specification